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1 April 2009 Defectivity process optimization on immersion topcoat less resist stacks
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Abstract
Demand for Immersion topcoat-less resist processes is being driven by the desire to reduce the cost per wafer pass. Two key characteristics, required by high speed immersion scanners, of topcoat-less resist are high receding contact angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results. In this paper the following will be presented: Defectivity results on 45nm L/S of several topcoat-less resists, including the effects of optimized track rinse recipes. Results of a fundamental study on static contact angles changes of different topcoat-less resists after each track process step to identify where in the process issues originate. Imaging and defectivity results of 38nm L/S using the topcoat-less champion resist are presented. These results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing 38 nm L/S in a single exposure .
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kazuhito Shigemori, Suping Wang, Len Tedeschi, Gazi Tanriseven, Raymond Maas, Coen Verspaget, Ruud Marechal, Ad Lammers, Joerg Mallmann, Masahiko Harumoto, Akihiro Hisai, and Masaya Asai "Defectivity process optimization on immersion topcoat less resist stacks", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72732B (1 April 2009); https://doi.org/10.1117/12.818745
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