Post exposure bake (PEB) is the most important process for chemically amplified resist to make nano-scale device.
According to 2007 ITRS roadmap, critical dimension (CD) should be controlled below 1.9 nm on sub-22 nm half
pitch in whole process of semiconductor. But CD error can be happened during the whole processes of exposure,
PEB, develop, and etching. For this study, we assumed PEB process is just one of four processes, so that we take
arithmetic mean error of four process, namely, ~ 0.5 nm (1.9 nm / 4) CD error should be controlled during PEB,
even though PEB is the critical processes for CD control. 1 degree PEB temperature difference would make 3 nm
CD change, so that we should control the temperature variation below 0.2 degree to control CD variation within 0.5
nm for 22 nm node. However, temperatures on the whole hot plate is not perfectly uniform. The temperature at the
heat source is higher than that at the position with no heat source. Such a temperature difference inside hot plate
would be directly transferred to the wafer and eventually inside the photoresist. Thus the temperature distribution
inside the whole photoresist would be non-uniform, and this would make non-uniform CD distribution eventually.
We calculated the temperature distribution within the hot plate in accordance with the position and structure of heat
source. We also calculated the temperature distribution inside photoresist by considering the heat conduction. In
addition to that, we estimated the possible CD variation caused by the non-uniform temperature distribution within
photoresist on wafer.