Feasibility studies of coating method for planarization process

Kentaro Matsunaga; Tomoya Oori; Hirokazu Kato; Eishi Shiobara; Makoto Muramatsu; Mitsuaki Iwashita; Takahiro Kitano; Yusuke Horiguchi; Tomoya Ohashi; Satoshi Takei; Shinichi Ito

doi:10.1117/12.813647

1 April 2009 Feasibility studies of coating method for planarization process

Kentaro Matsunaga, Tomoya Oori, Hirokazu Kato, Eishi Shiobara, Makoto Muramatsu, Mitsuaki Iwashita, Takahiro Kitano, Yusuke Horiguchi, Tomoya Ohashi, Satoshi Takei, Shinichi Ito

Author Affiliations +

Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 72734E (2009) https://doi.org/10.1117/12.813647
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

The lithography process on topographic substrate is one of the most critical issues for device manufacturing. Topographic substrate-induced focus variation occurs between top position and bottom position in a layer. That is, common depth of focus is reduced. This focus variation is sure to ruin the focus budget in low k1 lithography. From the focus budget of CMOS device, substrate topography is required to be less than 30nm for hp 45-nm generation devices and less than 15nm for hp 32-nm generation devices. In this paper, the authors evaluate a novel concept for hp45-nm generation dual damascene layer for global surface planarization. The novel concept is thin planarization layer with bottom anti-reflecting (BAR) function. This planarization layer with optical performance is materialized by UV crosslink materials and process. This concept is expected to lead to a simpler planarization process. Thin planarization layer with BAR function clear BARC layer and simplifies the etching process. Our study showed that the planarization performance of UV crosslink layer with 100nm thickness was 20nm thickness bias between the field area and dense via hole area. This thickness bias achieved the requirement of hp 45nm generation. Furthermore, fine resist pattern was resolved on the planarization layer by the optimization of acid components and additive.

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Kentaro Matsunaga, Tomoya Oori, Hirokazu Kato, Eishi Shiobara, Makoto Muramatsu, Mitsuaki Iwashita, Takahiro Kitano, Yusuke Horiguchi, Tomoya Ohashi, Satoshi Takei, and Shinichi Ito "Feasibility studies of coating method for planarization process", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72734E (1 April 2009); https://doi.org/10.1117/12.813647

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KEYWORDS

Ultraviolet radiation

Coating

Atomic force microscopy

Lithography

Materials processing

Critical dimension metrology

Semiconducting wafers

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