16 March 2009 Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process
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Abstract
We demonstrate experimentally for the first time the feasibility of applying SMO technology using pixelated illumination. Wafer images of SRAM contact holes were obtained to confirm the feasibility of using SMO for 22nm node lithography. There are still challenges in other areas of SMO integration such as mask build, mask inspection and repair, process modeling, full chip design issues and pixelated illumination, which is the emphasis in this paper. In this first attempt we successfully designed a manufacturable pixelated source and had it fabricated and installed in an exposure tool. The printing result is satisfactory, although there are still some deviations of the wafer image from simulation prediction. Further experiment and modeling of the impact of errors in source design and manufacturing will proceed in more detail. We believe that by tightening all kind of specification and optimizing all procedures will make pixelated illumination a viable technology for 22nm or beyond. Publisher's Note: The author listing for this paper has been updated to include Carsten Russ. The PDF has been updated to reflect this change.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kafai Lai, Alan E. Rosenbluth, Saeed Bagheri, John Hoffnagle, Kehan Tian, David Melville, Jaione Tirapu-Azpiroz, Moutaz Fakhry, Young Kim, Scott Halle, Greg McIntyre, Alfred Wagner, Geoffrey Burr, Martin Burkhardt, Daniel Corliss, Emily Gallagher, Tom Faure, Michael Hibbs, Donis Flagello, Joerg Zimmermann, Bernhard Kneer, Frank Rohmund, Frank Hartung, Christoph Hennerkes, Manfred Maul, Robert Kazinczi, Andre Engelen, Rene Carpaij, Remco Groenendijk, Joost Hageman, Carsten Russ, "Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process", Proc. SPIE 7274, Optical Microlithography XXII, 72740A (16 March 2009); doi: 10.1117/12.814680; https://doi.org/10.1117/12.814680
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