Double patterning (DP) was investigated for logic layout by using rigorous 3D wafer-topography/
lithography simulator with water immersion lithography. With increasing complexity of DP process,
3D wafer-topography effect of stack structure must be considered, because of its impact to
The main purpose of this paper is to present how to optimize both process and design to ensure
overlap and connectivity of split pattern, by solving electro-magnetic field distribution in wafer
substrate as well as resist region.
Process window was analyzed varying not only focus, dose and split masking layers, but also
considering topography of substrate stack structures, which cause local reflectivity variations.
Arbitrary 45nm logic layout including L-shape pattern was analyzed. Process window of second
Litho step was analyzed. Due to reflection from Hard Mask, HM (the first Litho step) the process
window was restricted and became smaller. The other option, swapping first and second Litho
masks is a better choice with respect to impact of wafer topography.
The optimization of stack process condition was analyzed by using contour plot of reflectivity, as
functions of n, k and thickness of materials inside BARC. The concept of Extended NILS
considering local reflectivity variation from wafer process is able to explain the variation of resist
sidewall slope and Exposure Latitude. Therefore, it is useful to analyze connectivity at stitching
point by using 3D wafer-topography/ lithography simulator and to optimize the combination of DP
process and layout stitching design. Furthermore as design of advanced process, LLE
(Litho-Litho-Etch), with resist freezing was simulated.