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16 March 2009 32nm and below logic patterning using optimized illumination and double patterning
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Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm pitch. It is likely that the node will begin at the upper end of the range, and then shrink by ~10% to a "28nm" node. For the lower end of the range, even with immersion scanners, the Rayleigh k1 factor is below 0.32. The 22nm logic node should begin with minimum pitches of approximately 70nm, requiring some form of double patterning to maintain k1 above 0.25. Logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete "freedom" compared to the very regular patterns used in memory. The logic layouts with bends and multiple pitches resulted in larger rules, un-optimized illumination, and a poorly understood process windows with little control of context-dependent "hot spots."[1] The introduction of logic design styles which use strictly one-directional lines for the critical levels now gives the opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give areacompetitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability.[2] These benefits can be extended to ≤32nm logic using selective double pass patterning.
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Michael C. Smayling and Valery Axelrad "32nm and below logic patterning using optimized illumination and double patterning", Proc. SPIE 7274, Optical Microlithography XXII, 72740K (16 March 2009);

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