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16 March 2009 Model-based scanner tuning in a manufacturing environment
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Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we explore using model simulations to characterize and predict imaging effects of these variables, and then based on such information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for 2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation. Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. Y. Shih, R. C. Peng, T. C. Chien, Y. W. Guo, J. Y. Lee, C. L. Chang, P. C. Huang, H. H. Liu, H. J. Lee, John Lin, K. W. Chang, C. P. Yeh, W. J. Shao, H. Cao, A. Bruguier, X. Xie, C. H. Chang, R. Aldana, Y. Cao, R. Goossens, and Simon Hsieh "Model-based scanner tuning in a manufacturing environment", Proc. SPIE 7274, Optical Microlithography XXII, 72740T (16 March 2009);

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