16 March 2009 Feasibility of ultra-low k1 lithography for 28nm CMOS node
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Abstract
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.
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Shoji Mimotogi, Kazuhiro Takahata, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Masaki Satake, Yosuke Kitamura, Tomoko Ojima, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Hiroki Yonemitsu, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Makoto Tominaga, Soichi Inoue, "Feasibility of ultra-low k1 lithography for 28nm CMOS node", Proc. SPIE 7274, Optical Microlithography XXII, 72741F (16 March 2009); doi: 10.1117/12.814040; https://doi.org/10.1117/12.814040
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