In the modern photolithography process for manufacturing integrated circuits, geometry dimensions need to
be realized on silicon which are much smaller than the exposure wavelength. Thus Resolution
Enhancement Techniques have an indispensable role towards the implementation of a successful
technology process node. Finding an appropriate RET recipe, that answers the needs of a certain
fabrication process, usually involves intensive computational simulations. These simulations have to reflect
how different elements in the lithography process under study will behave. In order to achieve this,
accurate models are needed that truly represent the transmission of patterns from mask to silicon.
A common practice in calibrating lithography models is to collect data for the dimensions of some test
structures created on the exposure mask along with the corresponding dimensions of these test structures on
silicon after exposure. This data is used to tune the models for good predictions.
The models will be guaranteed to accurately predict the test structures that has been used in its tuning.
However, real designs might have a much greater variety of structures that might not have been included in
the test structures.
This paper explores a method for compiling the test structures to be used in the model calibration process
using design layouts as an input. The method relies on reducing structures in the design layout to the
essential unique structure from the lithography models point of view, and thus ensuring that the test
structures represent what the model would actually have to predict during the simulations.