Layout electrical cooptimization for increased tolerance to process variations

Lionel Riviere-Cazaux; Philippe Hurat; Bala Kasthuri; Larry Layton; Nishath Verghese

doi:10.1117/12.813969

12 March 2009 Layout electrical cooptimization for increased tolerance to process variations

Lionel Riviere-Cazaux, Philippe Hurat, Bala Kasthuri, Larry Layton, Nishath Verghese

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 727506 (2009) https://doi.org/10.1117/12.813969
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

To address the variability challenges inherent to 45 and 32nm as early as possible, a model-based variability analysis has been implemented to predict lithography induced electrical variability in standard cell libraries, and this analysis was used optimize the cell layout and decrease variability by up to 40%.

Citation Download Citation

Lionel Riviere-Cazaux, Philippe Hurat, Bala Kasthuri, Larry Layton, and Nishath Verghese "Layout electrical cooptimization for increased tolerance to process variations", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727506 (12 March 2009); https://doi.org/10.1117/12.813969

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