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Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer
processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature.
Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are
layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical
effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA)
variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit
parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been
previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with
an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the
possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In
this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate
circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as
threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC
can be leveraged to compensate circuit performance for matching designer intent. Compared to existing
compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the
process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC
to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In
addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage
variability, which potentially translates to mitigation of circuit-limited yield.
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