Scaling of integrated circuits over the past several ten years has been done successfully by improvement of
photolithography equipment and resolution enhancement technique. The smaller the feature size is, the tighter
controllability of critical dimension (CD) is required. Enormous efforts have been made to achieve device specifications.
Especially in logic devices as system on chip, controllability of gate transistor CD is the one of the greatest concern for
both designer and manufacturer since characteristics of device chip, speed and power, are largely depend on the gate CD.
From the viewpoint of manufacturer all gate transistors on a chip have equivalent weight and tight CD controls are
applied to them. Nevertheless, each transistor has a various weight and required controllability is definitely different
from the viewpoint of chip designer. In this paper, we introduce the concepts of tolerance as representation of design
intentions. An intention derived at chip designing stage is converted to a formula which is comprehensive and
measurable at manufacturing1,2. Timing margin of each path, which is derived from timing analysis at chip design, can be
converted to the most comprehensive formula as CD tolerance, for instance. Two major application of the tolerance
deduced from design intention will be presented. The first one is reduction of OPC processing time and the second
application of the tolerance is qualification at photo-mask and wafer processing. Comprehension of design intentions and
interpretation of them to tolerance will be promising way for cost effective manufacturing.