12 March 2009 Practical implementation of via and wire optimization at the SoC level
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Abstract
In recent years, various DFM techniques are developed and adopted by the designers to improve circuit yield and reliability. The benefits from applying a DFM technique to a circuit often come at the expense of degrading other process or design attributes. In this paper, we discuss two widely deployed techniques: double vias and wire spreading/widening, show the benefits and trade-offs of their usage, and practical ways to implement them in SoC designs.
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Chi-Min Yuan, Chi-Min Yuan, Guy Assad, Guy Assad, Bob Jarvis, Bob Jarvis, Marc Olivares, Marc Olivares, Lionel Riviere Cazaux, Lionel Riviere Cazaux, Puneet Sharma, Puneet Sharma, Jayathi Subramanian, Jayathi Subramanian, Matt Thompson, Matt Thompson, Kevin Wu, Kevin Wu, } "Practical implementation of via and wire optimization at the SoC level", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750S (12 March 2009); doi: 10.1117/12.813396; https://doi.org/10.1117/12.813396
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