As the process development advances to deep sub-100 nm technology, many new
technologies such as immersion lithography and hyper NA lens design are developed for
the improved on-wafer pattern resolution to meet the technology requirement. During the
early process development such as 45 nm technology, it was not clear that lithography
tool could meet stringent CD variation requirement. Many rules such as fixed poly pitch,
single poly orientation, and dummy poly insertion for diffusion edge transistors were
implemented [1, 2] to ensure that, with designated litho-tool, the CD variation control
could be minimized. These rules generally added layout design complexity and area
penalty. It would be efficient that these rules could be evaluated and properly
implemented with data collected from well-design test structures.
In this work, a set of simple test structures with various dummy poly gate lengths
and numbers of dummy poly gates, and fix-pitch poly gate orientations were
implemented in the process development test vehicles (TV's). Electrical, simulation, and
in-line CD data of these test structures were collected. Analysis of the data and related
design rule optimization and implementation are described. This work helped to optimize and to properly implement the 45 nm gate poly
design rules during early process development for Xilinx FPGA product development.