The importance of Line Edge Roughness (LER) and Line Width Roughness (LWR) has long surpassed its
effect on process control. As devices scale down, the roughness effects have become a major hindrance for further
advancement along Moore's law. Many studies have been conducted over the years on the sensitivity of LER to various
changes in the materials and the process, which have been considered the main way to tackle the problem - especially
through Photoresist improvement. However, despite the increased development of DFM tools in recent years, limited
research was done as to LER sensitivity to layout, and the research that was done was limited to proximity effects.
In this paper, we study the sensitivity of LER to the layout around the transistor, defined by the gate structure
of poly over AA (Active Area). Using different types and geometries of transistors, we found that the poly-gate LER is
sensitive to the structure of the Active Area around it (source/drain from gate to contact, both shape and length). Using
local LER measurement (moving standard deviation of poly edge location), we found a clear correlation between LER
value and the length of the AA/STI boundary located at a close range. Longer AA edges yield higher LER, as proved by
comparing gate LER of dog-bone transistor with classical transistor. Based on these results, we suggest that LER is
sensitive not only to proximity effects, but also to the layout of underlying layers, through the effect of light scattering
of the edges during the lithographic process.