12 March 2009 Lithography aware statistical context characterization of 40nm logic cells
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Abstract
At the 40nm technology node, lithographic effects have a significant impact on the electrical characteristics of CMOS transistors, which directly affects the performance of circuits containing these devices. Many of these effects are systematic and intra-cell, and can therefore be accurately modeled by accounting for layout proximity effects during cell characterization. However, because the final cell placement for real designs is not known at the time of characterization, inter-cell proximity variations cannot be treated systematically at that time. We present a method to analyze inter-cell proximity variation statistically, and approximate the effect of context as a random variable during full chip verification. We then show an example analysis applied to standard logic cells in a 40nm technology.
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Mark E. Rubin, Naohiro Kobayashi, Toshiaki Yanagihara, "Lithography aware statistical context characterization of 40nm logic cells", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751C (12 March 2009); doi: 10.1117/12.814371; https://doi.org/10.1117/12.814371
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