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12 March 2009 Implementing self-aligned double patterning on non-gridded design layouts
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The Sidewall Spacer Double Patterning (SSDP) technique, also referred to as Self-Aligned Double Patterning (SADP), has been adopted as the primary double patterning solution for 32nm technology nodes and below for flash memory manufacturing. Many are now looking to migrate the technique to DRAM and random Logic layers. However, DRAM and especially Logic have far more complex layout requirements than NAND-FLASH, requiring a more sophisticated use of the SSDP technique. To handle the additional complexities an automated electronic design tool was used to calculate optimal layout splits of a design target into 2 or 3 masks. The model was programmed with immersion lithography and dry-193nm lithography MRC input rules and on wafer performance was tested. We discuss the patterning needs from the trim-mask and the pad-mask and associated lithography process window requirements and alignment accuracies necessary to pursue 32nm and 22nm half-pitch designs.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Huixiong Dai, Jason Sweis, Chris Bencher, Yongmei Chen, Jen Shu, Xumou Xu, Chris Ngai, Judy Huckabay, and Milind Weling "Implementing self-aligned double patterning on non-gridded design layouts", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751E (12 March 2009);

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