7 January 2009 Dual mode 1.25-2.5 Gb/s CMOS limiting amplifier circuit for optical receivers
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Proceedings Volume 7297, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies IV; 729721 (2009) https://doi.org/10.1117/12.823685
Event: Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies IV, 2008, Constanta, Romania
Abstract
A 1.25-2.5Gb/s burst-mode limiting amplifier for gigabit passive optical networks (GPON) is presented in this paper. It supports both PIN-PD and APD diodes. A response time of 5 ns and sensitivity of 4 mVpp is achieved by introducing a modified amplified stage with active feedback and negative Miller capacitance compensation techniques. This circuit operates with a supply voltage 3 V and it is fabricated in 180 nm CMOS technology. The influence of the parasitic layout elements and their effects on the performance of the limiting amplifier will be illustrated using RC and RLC parasitic extraction and simulation results.
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Cristian M. Albina, "Dual mode 1.25-2.5 Gb/s CMOS limiting amplifier circuit for optical receivers", Proc. SPIE 7297, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies IV, 729721 (7 January 2009); doi: 10.1117/12.823685; https://doi.org/10.1117/12.823685
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