28 April 2009 A 1.28GSPS 12-bit optoelectronic analog-to-digital converter
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A 1.28GSPS 12-bits optoelectronic analog-to-digital converter is presented. The ADC architecture consists of an optical circuit that optically samples an analog input signal, and optoelectronic circuits that demultiplex different phases of the sampled signal (polyphase) to yield low data rate for electronic quantization. Electrical-in to electrical-out data format is maintained through the sampling, demultiplexing and quantization stages of the architecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. The ADC architecture encodes and multiplexes four 320MSPS 12-bits time interleaves quantized data into an aggregated 1.28GSPS 12-bits digital signal in real time. All clock signals at frequencies of 1.28GHz, 640MHz, and 320MHz are generated from a single 320MHz femtosecond laser source, thus eliminating the need for external synchronization and control signals. A Spurious Free Dynamic Range (SFDR) of value 80.6dB, and Effective number of bits (ENOB) of value 8.8 bits, were measured for the system.
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Carlos Villa, Carlos Villa, Patrick Kumavor, Patrick Kumavor, Eric Donkor, Eric Donkor, Guanghai Jin, Guanghai Jin, } "A 1.28GSPS 12-bit optoelectronic analog-to-digital converter", Proc. SPIE 7339, Enabling Photonics Technologies for Defense, Security, and Aerospace Applications V, 73390G (28 April 2009); doi: 10.1117/12.819454; https://doi.org/10.1117/12.819454

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