1 May 2009 Structured low-density parity-check codes with bandwidth efficient modulation
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In this work, we study the performance of structured Low-Density Parity-Check (LDPC) Codes together with bandwidth efficient modulations. We consider protograph-based LDPC codes that facilitate high-speed hardware implementations and have minimum distances that grow linearly with block sizes. We cover various higherorder modulations such as 8-PSK, 16-APSK, and 16-QAM. During demodulation, a demapper transforms the received in-phase and quadrature samples into reliability information that feeds the binary LDPC decoder. We will compare various low-complexity demappers and provide simulation results for assorted coded-modulation combinations on the additive white Gaussian noise and independent Rayleigh fading channels.
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Michael K. Cheng, Michael K. Cheng, Dariush Divsalar, Dariush Divsalar, Stephanie Duy, Stephanie Duy, } "Structured low-density parity-check codes with bandwidth efficient modulation", Proc. SPIE 7349, Wireless Sensing and Processing IV, 73490C (1 May 2009); doi: 10.1117/12.818223; https://doi.org/10.1117/12.818223


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