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4 May 2009 An FPGA-based design of a modular approach for integral images in a real-time face detection system
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The first step in a facial recognition system is to find and extract human faces in a static image or video frame. Most face detection methods are based on statistical models that can be trained and then used to classify faces. These methods are effective but the main drawback is speed because a massive number of sub-windows at different image scales are considered in the detection procedure. A robust face detection technique based on an encoded image known as an "integral image" has been proposed by Viola and Jones. The use of an integral image helps to reduce the number of operations to access a sub-image to a relatively small and fixed number. Additional speedup is achieved by incorporating a cascade of simple classifiers to quickly eliminate non-face sub-windows. Even with the reduced number of accesses to image data to extract features in Viola-Jones algorithm, the number of memory accesses is still too high to support realtime operations for high resolution images or video frames. The proposed hardware design in this research work employs a modular approach to represent the "integral image" for this memory-intensive application. An efficient memory manage strategy is also proposed to aggressively utilize embedded memory modules to reduce interaction with external memory chips. The proposed design is targeted for a low-cost FPGA prototype board for a cost-effective face detection/recognition system.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hau T. Ngo, Ryan N. Rakvic, Randy P. Broussard, and Robert W. Ives "An FPGA-based design of a modular approach for integral images in a real-time face detection system", Proc. SPIE 7351, Mobile Multimedia/Image Processing, Security, and Applications 2009, 73510B (4 May 2009);

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