28 May 2009 Method for run time hardware code profiling for algorithm acceleration
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Proceedings Volume 7363, VLSI Circuits and Systems IV; 736304 (2009); doi: 10.1117/12.821704
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany
Abstract
In this paper we propose a method for run time profiling of applications on instruction level by analysis of loops. Instead of looking for coarse grain blocks we concentrate on fine grain but still costly blocks in terms of execution times. Most code profiling is done in software by introducing code into the application under profile witch has time overhead, while in this work data for the position of a loop, loop body, size and number of executions is stored and analysed using a small non intrusive hardware block. The paper describes the system mapping to runtime reconfigurable systems. The fine grain code detector block synthesis results and its functionality verification are also presented in the paper. To demonstrate the concept MediaBench multimedia benchmark running on the chosen development platform is used.
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Vladimir Matev, Eduardo de la Torre, Teresa Riesgo, "Method for run time hardware code profiling for algorithm acceleration", Proc. SPIE 7363, VLSI Circuits and Systems IV, 736304 (28 May 2009); doi: 10.1117/12.821704; https://doi.org/10.1117/12.821704
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KEYWORDS
Field programmable gate arrays

Profiling

Control systems

Detection and tracking algorithms

Multimedia

Clocks

Logic

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