Parallel workload analysis in SMP platform: a new modelling approach to infer the hardware efficiency for remote sensing application

Guo Yi; Eleni Kanellou; L. Andrés Cardona; Antonio Rius; Carles Ferrer

doi:10.1117/12.821549

28 May 2009 Parallel workload analysis in SMP platform: a new modelling approach to infer the hardware efficiency for remote sensing application

Guo Yi, Eleni Kanellou, L. Andrés Cardona, Antonio Rius, Carles Ferrer

Author Affiliations +

Proceedings Volume 7363, VLSI Circuits and Systems IV; 736308 (2009) https://doi.org/10.1117/12.821549
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

The remote sensing techniques have put great pressure on real-time waveform post-processing design. Due to the intensive computation and multi-channel waveform integration, the overhead between the processing time and the storage of amount of data prior to downlink issues has lead us to get the solution of task-level parallelism. With the development of IC design and innovation of architecture, embedded system can range from a single microprocessor to a complex multi-processor and even including the embedded operating system (OS) on a chip. Therefore symmetric multiprocessing (SMP) with embedded OS offers an attractive way to expose coarse-grained parallelism application. In this paper we demonstrate a new modeling approach. In order to simplify the system; a workload model is derived from a remote sensing application, which represents the workload characteristic and time degrading factors. The intention is to leverage the task-level parallelism load is evenly to each processor in SMP, with the OS level testing to speculate the bottleneck in hardware level. This parallel workload model which maps to a 6-LEON3 SMP architecture, attains a 2.7x mean speedup over a single-LEON3 baseline; with 3-LEON3 attains a 2.23x mean speedup; with 2- LEON3 attains a 1.78x mean speedup over a single-LEON3 baseline. Due to the involved sharing resources and scheduling of multiple CPUs, the system will have a degrading in processing speed. With this lag we could infer the hardware pipeline efficiency. And afford on the processor-set subsystem and memory subsystem analysis reveal the affects on the system throughput.

Citation Download Citation

Guo Yi, Eleni Kanellou, L. Andrés Cardona, Antonio Rius, and Carles Ferrer "Parallel workload analysis in SMP platform: a new modelling approach to infer the hardware efficiency for remote sensing application", Proc. SPIE 7363, VLSI Circuits and Systems IV, 736308 (28 May 2009); https://doi.org/10.1117/12.821549

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