22 May 2009 Enabling accurate gate profile control with inline 3D-AFM
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Proceedings Volume 7378, Scanning Microscopy 2009; 73781G (2009) https://doi.org/10.1117/12.824203
Event: SPIE Scanning Microscopy, 2009, Monterey, California, United States
The logic and memory semiconductor device technology strives to follow the aggressive ITRS roadmap. The ITRS calls for increased 3D metrology to meet the demand for tighter process control at 45nm and 32nm nodes. In particular, gate engineering has advanced to a level where conventional metrology by CD-SEM and optical scatterometry (OCD) faces fundamental limitations without involvement of 3D atomic force microscope (3D-AFM or CD-AFM). This paper reports recent progress in 3D-AFM to address the metrology need to control gate dimension in MOSFET transistor formation. 3D-AFM metrology measures the gate electrode at post-etch with the lowest measurement uncertainty for critical gate geometry, including linewidth, sidewall profile, sidewall angle (SWA), line width roughness (LWR), and line edge roughness (LER). 3D-AFM enables accurate gate profile control in three types of metrology applications: reference metrology to validate CD-SEM and OCD, inline depth or 3D monitoring, or replacing TEM for 3D characterization for engineering analysis.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tianming Bao, Tianming Bao, Andrew Lopez, Andrew Lopez, Dean Dawson, Dean Dawson, "Enabling accurate gate profile control with inline 3D-AFM", Proc. SPIE 7378, Scanning Microscopy 2009, 73781G (22 May 2009); doi: 10.1117/12.824203; https://doi.org/10.1117/12.824203

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