11 May 2009 Inspection and repair for imprint lithography at 32 nm and below
Author Affiliations +
Proceedings Volume 7379, Photomask and Next-Generation Lithography Mask Technology XVI; 73790N (2009); doi: 10.1117/12.824264
Event: Photomask and NGL Mask Technology XVI, 2009, Yokohama, Japan
Step and Flash Imprint involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the progress made in inspection and repair of 1X imprint masks A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. These defects were then inspected using three different electron beam inspection systems. Defect sizes as small as 8 nm were detected, and detection limits were found to be a function of defect type. Both subtractive and additive repairs were attempted on SRAM Metal 1 cells. Repairs as small as 32nm were demonstrated, and the repair process was successfully tested for several hundreds of imprints.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kosta Selinidis, Ecron Thompson, S. V. Sreenivasan, Douglas J. Resnick, Marcus Pritschow, Joerg Butschke, Mathias Irmscher, Holger Sailer, Harald Dobberstein, "Inspection and repair for imprint lithography at 32 nm and below", Proc. SPIE 7379, Photomask and Next-Generation Lithography Mask Technology XVI, 73790N (11 May 2009); doi: 10.1117/12.824264; https://doi.org/10.1117/12.824264




Defect detection


Semiconducting wafers

Scanning electron microscopy

Back to Top