In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight
non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for
Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To
meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield
and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the
reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the
specifications to be relaxed.
In this paper, we will present the results of using e-beam image placement corrections during mask writing to
compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness
was employed. Three different compensation methods were used to calculate the predicted image placement
errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed
to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark
was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks
were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction
methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.