A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an
introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage
down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic
manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop
process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to
define critical layers with double photolithography and etch process becomes increasingly evident.
Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D
features is so challenging that opposing line-ends can only be defined using an additional litho and etch
step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit.
Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning
technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and
then successfully decomposed, so an additional set of restrictions is required to make layouts double
patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that
they can be patterned using both masks. The electric performance of this cut circuitry may be highly
dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to
misalignment between the two patterning steps. We used representative logic layouts of metal level and
realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend
splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink
approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of
parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned
using double patterning aware OPC and printability verification tools.