4 August 2009 Design of readout circuit for microcantilever infrared focal plane array with snapshot integration
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Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50μm and capacitive trans-impedance amplifier is used in pixel stage for low noise and high linearity. A 800fF storage capacitor is implemented in each pixel for snapshot imaging. The pixel OTAs are powered off during pixel signals readout phase and master-slave buffer method is employed in column readout stage and output buffer stage for low power. The 160x120 ROIC has been designed and simulated for 50Hz frame frequency with one output port. The pixel rate is 1MHz, charge handling capacity is 1.5x105 electrons, pixel linearity is as high as 99.9% and the power consumption is less than 20mw. A 16x16 experimental chip has been designed, post-simulated and manufactured with a 0.35μm CMOS DPTM technology and is being tested.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ke Lei, Ke Lei, Zhongjian Chen, Zhongjian Chen, Junmin Cao, Junmin Cao, Yaciong Zhang, Yaciong Zhang, Wengao Lu, Wengao Lu, Lijiu Ji, Lijiu Ji, } "Design of readout circuit for microcantilever infrared focal plane array with snapshot integration", Proc. SPIE 7383, International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications, 73833L (4 August 2009); doi: 10.1117/12.836613; https://doi.org/10.1117/12.836613


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