4 August 2009 Design and test results of a readout circuit for high energy particle detectors
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A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output stage. The readout circuit has been designed in a 0.35um DPTM CMOS technology and tested with Verigy 93000. The size of readout circuit is 1.7*0.7mm2. The power supply voltage is 5V. The average gain is about 20.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 550-650e for five chips in the typical mode. The power dissipation is about 8mW and 2mW respectively, with and without output buffer. The linearity reaches 99.2% in the typical mode. The gain is tunable from 13mV/fC to 130mV/fC and the peaking time varies from 700ns to 1.6us.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mingming Zhang, Mingming Zhang, Zhongjian Chen, Zhongjian Chen, Yacong Zhang, Yacong Zhang, Wengao Lu, Wengao Lu, Huiyao An, Huiyao An, Lijiu Ji, Lijiu Ji, } "Design and test results of a readout circuit for high energy particle detectors", Proc. SPIE 7385, International Symposium on Photoelectronic Detection and Imaging 2009: Terahertz and High Energy Radiation Detection Technologies and Applications, 73851N (4 August 2009); doi: 10.1117/12.836618; https://doi.org/10.1117/12.836618


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