17 September 2009 Fundamental performance differences between CMOS and CCD imagers: part III
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This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James Janesick, James Janesick, Jeff Pinter, Jeff Pinter, Robert Potter, Robert Potter, Tom Elliott, Tom Elliott, James Andrews, James Andrews, John Tower, John Tower, John Cheng, John Cheng, Jeanne Bishop, Jeanne Bishop, } "Fundamental performance differences between CMOS and CCD imagers: part III", Proc. SPIE 7439, Astronomical and Space Optical Systems, 743907 (17 September 2009); doi: 10.1117/12.831203; https://doi.org/10.1117/12.831203


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