23 September 2009 Mask performance improvement with mapping
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Current high end chips require an extremely precise fabrication of lithographic masks. Some of the most critical parameters are the placement of structures on the masks as well as their dimensional tolerances. Improving these two key parameters has always been one of the central objectives of the Advanced Mask Technology Center (AMTC). To this end, the AMTC has complemented its process development by a set of enhancement schemes which are used to compensate residual process signatures. In this paper, improvements achieved in the area of CD uniformity (CDU) and pattern placement are shown. The correction schemes take first principle considerations as well as empirical findings into account. Based on this, a set of design and process parameters is used to determine the spatial corrections which will optimize mask quality parameters. This enables the AMTC to tailor the writing parameters to the needs of each mask design. Latest results for the 32nm technology show that values as low as 5nm image placement error and 3nm CDU can be reached at the same time.
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Clemens Utzny, Clemens Utzny, Eric Cotte, Eric Cotte, Timo Wandel, Timo Wandel, Jan Hendrik Peters, Jan Hendrik Peters, "Mask performance improvement with mapping", Proc. SPIE 7488, Photomask Technology 2009, 74880N (23 September 2009); doi: 10.1117/12.834302; https://doi.org/10.1117/12.834302

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