This PDF file contains the front matter associated with SPIE Proceedings Volume 7520, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

As the development cost of a typical system-on-chip (SOC) using state-of-the-art technology soars, more and more people turn to three-dimensional (3D) integration for possible alternatives that provide better or equal performance with lower cost. Stacking dies using the through-silicon-via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this paper we will discuss the opportunities, design and manufacturing issues, and possible solutions for 3D integrated devices, from a designer's perspective.

Not long after the photon beam was used to delineate circuit patterns in resist, e-beam was called for duty due to the concern of photons running out of resolution. The e-beam counterpart of proximity printing, projection printing, and direct writing quickly took shape as early as 1975. The race was on. Optical projection printing, taking advantage of a high degree of parallelism, excelled in throughput and economy for wafer patterning. However, electrons can be quickly deflected to directly write patterns. It took over mask writing. Rivalry turned into complementary for decades. Recently e-beam has a new opportunity to beat photon beam at its own game of parallelism and eliminate the problems associated with masks altogether. This presentation compares optical and e-beam imaging technically, economically, and historically, pointing to the rewards and challenges for each technology to succeed.

Extreme ultraviolet (EUV) technology has been recognized as the major lithography technology for 22 nm HP and beyond to fulfill Moore's Law, which predicts that circuit dimensions shrink 70% every 2~3 years in order to achieve cost down and obtain greater functionality per unit area. EUV source power is one of the key factors in determining the cost-effectiveness of EUVL compared to other lithography technologies, like double patterning. Only when EUV power can achieve a certain level, the cost of EUV lithography under high volume manufacturing (HVM) can become much more competitive than that of double patterning techniques. In this paper, the performance of the first production Cymer high power laser produced plasma (LPP) EUV source integrated with a 5 sr multi-layer mirror (MLM) collector and fully integrated debris mitigation will be shown. The latest results on power generation, stable and efficient collection, and clean transmission of EUV light through the intermediate focus will be presented. The lifetime of the MLM collector is a critical parameter in the development of extreme ultraviolet LPP lithography sources. Debris mitigation techniques are used to inhibit reflectivity degradation from deposition of target material, sputtering of the multilayer coating, and implantation of incident particles, which can reduce the efficiency of the MLM collector during exposure. The far field images of MLM collector are recorded by intermediate focus metrology with a CCD camera to determine the reflectivity status of the MLM collector during exposure. The results of these debris mitigation techniques are compared through multiple-hour EUV exposure. Testing shows cleanliness at the source-scanner interface acceptable to the limit of detection.

Cost, cost, cost: that is what it is - ultimately - all about. Single exposure lithography is the most cost effective means of achieving critical level exposures, and extreme ultraviolet lithography (EUVL) is the only technology that will enable this for ≤ 27nm production. ASML is actively engaged in the development of a multi-generation production EUVL system platform that builds on TWINSCAN^TM technology and the designs and experience gained from the Alpha Demo Tools (ADTs). The ADTs are full field step-and-scan exposure systems for EUVL and are being used at two research centers for EUVL process development by more than 10 of the major semiconductor chip makers, along with all major suppliers of masks and resist. Recently, successful implementation of EUVL for the contact hole and metal layer was demonstrated in the world's smallest (0.099 μm²) electrically functional 22nm CMOS SRAM device [1]. We will highlight the key features of the system description for the production platform, including the manufacturing status of projection lens, illuminator optics, and source. Experimental results from ADT showing the progress in imaging and resist work will be covered as well - a snapshot of imaging data can be seen in the figure below. We will share our vision on the extendability of EUVL by discussing our system implementation roadmap. We will explain our approach for multiple tool generations on a single platform, highlighting the ways to support the technology nodes from 27nm half-pitch with a 0.25NA lens going down to below 16nm with a 0.32NA lens.

E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour (WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of beams, switching them on and off independently. The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including illumination, focusing, and CD uniformity, are discussed.

Organic flexible electronics is an emerging technology with huge potential growth in the future which is likely to open up a complete new series of potential applications such as flexible OLED-based displays, urban commercial signage, and flexible electronic paper. The transistor is the fundamental building block of all these applications. A key challenge in patterning transistors on flexible plastic substrates stems from the in-plane nonlinear deformations as a consequence of foil expansion/shrinkage, moisture uptake, baking etc. during various processing steps. Optical maskless lithography is one of the potential candidates for compensating for these foil distortions by in-situ adjustment prior to exposure of the new layer image with respect to the already patterned layers. Maskless lithography also brings the added value of reducing the cost-of-ownership related to traditional mask-based tools by eliminating the need for expensive masks. For the purpose of this paper, single-layer maskless exposures at 355 nm were performed on gold-coated poly(ethylenenaphthalate) (PEN) flexible substrates temporarily attached to rigid carriers to ensure dimensional stability during processing. Two positive photoresists were employed for this study and the results on plastic foils were benchmarked against maskless as well as mask-based (ASML PAS 5500/100D stepper) exposures on silicon wafers.

Recent publications have emphasized the criticality of computational lithography in source-mask selection for 32 and 22 nm technology nodes. Lithographers often select the illuminator geometries based on analyzing aerial images for a limited set of structures using computational lithography tools. Last year, Biafore, et al¹ demonstrated the divergence between aerial image models and resist models in computational lithography. In a follow-up study², it was illustrated that optimal illuminator is different when selected based on resist model in contrast to aerial image model. In the study, optimal source shapes were evaluated for 1D logic patterns using aerial image model and two distinct commercial resist models. Physics based lumped parameter resist model (LPM) was used. Accurately calibrated full physical models are portable across imaging conditions compared to the lumped models. This study will be an extension of previous work. Full physical resist models (FPM) with calibrated resist parameters^3,4,5,6 will be used in selecting optimum illumination geometries for 1D logic patterns. Several imaging parameters - like Numerical Aperture (NA), source geometries (Annular, Quadrupole, etc.), illumination configurations for different sizes and pitches will be explored in the study. Our goal is to compare and analyze the optimal source-shapes across various imaging conditions. In the end, the optimal source-mask solution for given set of designs based on all the models will be recommended.

In low-k1 lithography, it is difficult to keep pattern fidelity and contrast for all features in one layer. Source mask optimization (SMO) software provide solutions to keep pattern fidelity and contrast for the selected critical patterns. We have developed SMO software, and study the efficiency of the software. In this paper, we show, SMO software is effective for current 45 nm node SRAM cell layers (Active, Gate and Metal). In addition, SMO is also effective for cutting lithography technology. Cutting lithography is expected to apply 22 nm half pitch process and beyond.

The co-optimization of the source and mask patterns [1, 2] is vital to future advanced ArF technology node development. This paper extends work previously reported on this topic [3, 4]. We will systematically study the impact of source on designs with different k₁ values using SMO. Previous work compared the co-optimized versus iterative source-mask optimization methods [3]. We showed that the co-optimization method clearly improved lithography performance. This paper's approach consists of: 1) Co-optimize a pixelated freeform source and a continuous transmission gray tone mask based on a user specified cost function; 2) ASML-certified scanner-specific models and constraints are applied to the optimized source; 3) Assist feature (AF) "seeds" are identified from the optimized continuous transmission mask (CTM). Both the AF seed and the main feature are subsequently converted into a polygon mask; 4) The extracted AF seeds and main features are co-optimized with the source to achieve the best lithographic performance. Using this approach, we first use a DRAM brick wall design to demonstrate that using the same cost function metric by adjusting the optimization conditions creates an image log slope only optimization that can easily be applied. An optimize design for imaging methodology is introduced and shown to be important for low k₁ imaging. A typical 2x node SRAM design is used to illustrate an integrated SMO design rule optimization flow. We use the same SRAM layout that used design rule optimization to study the source complexity impact with a range of k₁ values that varies from 0.42 to 0.35. For the source type, we use freeform and traditional finite pole shape DOEs, all subject to ASML's scanner-specific models and constraints. We report the process window, MEF and process variation band (PV band) with different source types to find which source type give the best lithography performance.

Mask manufacturability has been considered as a major issue in the adoption of inverse lithography (IL) in practice. With smaller technology nodes, IL distorts the mask pattern more aggressively. The distorted mask often contains curvilinear contour and irregular shapes, which cast a heavy computation burden on segmentation and data preparation. Total variation (TV) has been used for regularization in previous work, but it is not very effective in regulating the mask shape to be rectangular. In this paper, we apply TV regularization not only on the mask image but also on the mask edges, which forces the curves of edges to be more vertical or horizontal, because they give smaller TV values. Except for rectilinearity, a group of geometrical specifications of the mask pattern set by mask manufacture rule control (MRC) is also important for mask manufacturability. To prevent these characteristics from appearing, we also propose an intervention scheme into the optimization framework.

The continuous shrinkage in dimensions of microelectronic devices has reached such level, with typical gate length in advance R&D of less than 20nm combine with the introduction of new architecture (FinFET, Double gate...) and new materials (porous interconnect material, 193 immersion resist, metal gate material, high k materials...), that new process parameters have to be well understood and well monitored to guarantee sufficient production yield in a near future. Among these parameters, there are the critical dimensions (CD) associated to the sidewall angle (SWA) values, the line edge roughness (LER) and the line width roughness (LWR). Thus, a new metrology challenge has appeared recently and consists in measuring "accurately" the fabricated patterns on wafers in addition to measure the patterns on a repeatable way. Therefore, a great effort has to be done on existing techniques like CD-SEM, Scatterometry and 3D-AFM in order to develop them following the two previous criteria: Repeatability and Accuracy. In this paper, we will compare the 3D-AFM and CD-SEM techniques as a mean to measure LER and LWR on silicon and 193 resist and point out CD-SEM impact on the material during measurement. Indeed, depending on the material type, the interaction between the electron beam and the material or between the AFM tip and the material can vary a lot and subsequently can generate measurements bias. The first results tend to show that depending on CD-SEM conditions (magnification, number of acquisition frames) the final outputs can vary on a large range and therefore show that accuracy in such measurements are really not obvious to obtain. On the basis of results obtained on various materials that present standard sidewall roughness, we will show the limit of each technique and will propose different ways to improve them in order to fulfil advance roadmap requirements for the development of the next IC generation.

Double patterning technology is capable of extending usability of immersion ArF systems for 32nm half-pitch node and below. However, overlay errors between the two patterning steps will directly contribute to critical dimension variation in a dual litho-etch process. The overlay errors need to be reduced significantly to meet the tight critical dimension uniformity requirement in the technology nodes. The present scanners are able to correct intra- and inter-field overlay errors that include not only linear terms but also certain higher-order terms. As a result, a 3nm overlay requirement for DPT becomes feasible by applying the most advanced correction schemes. Overlay modeling with a larger number of sample fields will give a more accurate estimate of the model parameters and will therefore improve the overlay corrections; however, metrology time will increase simultaneously. To balance the correction accuracy and metrology time, the number of fields and its layout on the wafer must be optimized. This also applies to wafer alignment, one of the other factors that determine the overlay performance. A bad alignment sampling scheme will cause a poor overlay performance in the end. Increasing the number of sample fields can improve the alignment performance but wafer throughput will be impacted immediately. Performance of the intra-field correction is dependent on number and distribution of the markers within an exposure field. Correction per field, for instance, is one of the most effective correction schemes. However, it needs to measure extra markers in each field for overlay modeling especially when including high-order terms. To limit the chip area occupied by the markers and the metrology time, it is necessary to well control the number of the markers. Moreover, accuracy of the overlay models is sensitive to layout of the markers. The overlay marker layout hence needs to be optimized to gain a robust correction with a minimum number of markers. In this paper, firstly we developed various geometry-based sampling methods for both alignment and overlay corrections to evaluate correction robustness while keeping the number of sample fields as small as possible. The results show that modeling with a limited number of fields can adequately describe a full-wafer alignment/overlay signature and the errors can be well corrected accordingly. A hybrid sampling approach was then proposed taking into consideration the spatial coverage (geometry-based) as well as the overlay signature of the fields. To improve the intra-field correction, an algorithm to assist in designing the layout of the overlay markers on a mask was developed. The most effective marker layouts with the least number of markers were suggested for different correction schemes. Using the most effective correction scheme as well as the proposed optimization techniques, the overlay performance can be improved to meet the overlay requirement of the 32nm DPT.

Patterned media is expected to be implemented in future generations of hard disk drives to provide data storage at densities exceeding 10¹² bits/in² and beyond. The implementation of patterned media, which would involve developing processing methods to offer high resolution (small bits), regular patterns, and high density, has posed a number of metrology challenges. Optical Critical Dimension (OCD) is the leading candidate to overcome the metrology challenges for patterned media. This paper presents the successful OCD measurements on the critical dimensions, sidewall-angles, and detailed sidewall shape of gratings of quartz template and imprint disk with pitch as small as 57nm.

With pitches in the double-digit nanometer range and depths in the single-digit nanometer range, superior sensitivity is a necessary metrology requirement for patterned media. Variations in depth, CD, and sidewall angle on the order of the desired measurement precision will change the measured raw data by a miniscule amount, around one per cent or less. It is shown that the required sensitivity can be achieved with polarized broad band reflectance and transmittance incorporating optimized signal-to-noise and analysis based on Rigorous Coupled-Wave Analysis (RCWA) in conjunction with the Forouhi-Bloomer dispersion equations for optical properties, n and k. The measurement capabilities are demonstrated with simulations and examples of various DTR and BPM structures.

In this study, a 3x-nm after development inspection (ADI) wafer with focus exposure matrix (FEM) was inspected with both an advanced optical system and an advanced EBI system, and the inspection results were carefully examined. We found that EBI can capture much more defects than optical system and it also can provide more information about within reticle shot defect distribution. It has high capture rate of certain critical defects that are insensitive to optical system, such as nano-bridges.

Extreme Ultraviolet (EUV) Lithography is currently viewed as the most promising approach for reaching the 22 nm node in the manufacture of silicon devices. One of the principal challenges in the ongoing EUVL research effort is the development of necessary at-wavelength metrology tools. EUV Technology worlds leading manufacturer of EUV metrology tools manufactures custom instrumentation for the utilization and analysis of short wavelength electromagnetic radiation - soft x-rays and extreme ultraviolet (EUV). Our company has pioneered the development of several stand-alone inspection, metrology, and calibration tools for EUV lithographic applications that can be operated in a clean room environment on the floor of a fab. An overview of necessary metrology tools for EUV Lithography will be presented, along with the challenges in developing these tools in order to support the successful implementation of EUV Lithography for the 22nm node. In addition, a detailed description of the EUV metrology tools we have delivered, their long term performance and stability of these tools along with our plans for developing a Reflectometer to achieve the HVM requirements will be discussed.

Image reversal trilayer (IRT) combines three lithographic patterning enhancement approaches: image reversal, spin on hard masks, and shrink for recess types of features. With IRT, photoresist imaging is done directly on top of the carbon underlayer. Thick IRT-Carbon Hard Masks (CHM) films provide effective antireflection with high NA lithography and are more etch resistant than common photoresist. IRT-Silicon Hard Masks (SiHM) can be coated over the resist patterns in the lithography track. IRT etching reverses the resist pattern into the IRT-SiHM and transfers this image to the IRTCHM. The recessed patterns in the IRT-CHM are smaller than the CD of the photoresist feature from an inherent shrinking capability of the IRT-SiHM. Continuous improvements to both IRT-SiHM and IRT-CHM have been made. Silicon contents in IRT-SiHM have been pushed as high as possible while not impacting other important properties such as stability, coating quality and resist compatibility. Newer polysiloxane IRT-SiHM no longer require resist freezing prior to coating. Carbon contents in IRTCHM have been pushed as high as possible while maintaining solubility and a low absorption which is important when resist imaging is done directly on top of the IRT-CHM. Feasibility of this image reversal trilayer process was previously demonstrated on L/S and pillar gratings. Recent work focused on nonsymmetrical 2D gratings and simultaneous patterning of L/S gratings at different pattern densities. Particular emphasis is given to pattern density effects which are applicable to any top-coating image reversal process. This paper describes the lithography, pattern transfer process and 2nd generation hard mask materials developed for IRT processing.

Many approaches to double patterning have been devised, of which most have been designed to reduce the number of process steps. The litho-freeze-litho-etch process (LFLE) is one such technique that eliminates the first etch step from the standard litho-etch litho-etch (LELE) process. The resist freeze material chemically modifies the patterned photoresist, as well as potentially the layer beneath, which may result in a performance change at the second lithography step. Another approach, litho-process-litho-etch (LPLE) does not involve the use of a chemical freeze material, instead relying on a thermal treatment to remove excess solvent from the polymer and differential energy of activation between two resists to create a double-patterned image. Finally, double patterning using negative-tone development of a positiveacting photoresist is another approach in consideration. In this paper, we present the results of several double-patterning processes on organic bottom anti-reflective coatings (BARCs) and spin-on multilayer stacks consisting of a silicon hardmask on top of a carbon underlayer. Pattern profiles of the first and second lithography steps are compared.

Developable bottom anti-reflective coatings (DBARC) are an emerging litho material technology. The biggest advantage of DBARC is that it eliminates the plasma etch step, avoiding damage to plasma sensitive layers during implantation. AZ has pioneered developable BARC based on photosensitive cleave as well as crosslink/decrosslink mechanisms. In this paper, we focus on the crosslink/decrosslink concept. DBARC/resist mismatching was corrected both from process and formulation sides. The optimized DBARC showed comparable lithographic performance as conventional BARCs. This paper provides the chemical concept of the photosensitive developable DBARCs, approaches for DBARC/resist matching and performance of photosensitive DBARCs for 248 nm and 193 nm exposures. Recent 193 nm immersion exposure results are also presented.

As IC manufactures explore different paths to meet the resolution requirements for next generation technology, patterning schemes which utilize a double photoresist patterning process are under extensive evaluation. One dual patterning process under consideration uses a 172nm UV cure to render the first photoresist pattern insoluble to the casting solvents and developer chemistries used to define the second photoresist pattern. Line-space resist patterning is used to understand the effect of the 172nm UV light on the SiBARC, under-layer film stack and how it influences the patterned CD. This is followed by cross-grid and pitch-split double patterning using 172 nm UV light of varying dose to freeze the first photoresist layer patterned using a tri-layer film configuration. In the final section we discuss the effects of the 172nm UV cure on the SiBARC film thickness and optical properties. Simulations are run to understand the change in the focus-exposure process window due to changes in the SiBARC film due to the 172nm UV cure.

Recent advances in EUVL lithography is mainly centered on improving the RLS trade-off by employing new resist platforms, bulkier PAGs, EUV sensitizers etc. Among the several new kinds of PAGs proposed till date, the focus of development was mainly on the acid strength, compatibility with resin etc., whilst always retaining the mono, Di or tri phenyl chromophore of the PAG. Herein we report on the use of chromophore-less PAG for the patterning of EUVL resists. Resist performance using model acrylate and PHS based resist was studied. The patterned resists were characterized using SEM. Thermal stability of the PAG was compared with model chromophore containing PAG.

Extreme ultraviolet (EUV) lithography is one of the promising candidates for device manufacturing with features smaller than 22 nm. Unlike traditional optical projection systems, EUV light needs to rely on reflective optics and masks with an oblique incidence for image formation in photoresist. The consequence of using a reflective projection system can result in horizontal-vertical (H-V) bias and pattern shift, which are generally referred as shadowing. Approaches proposed to compensate for shadowing effect include changing mask topography, modifying mask focus, and biasing features along the azimuth angle, which are all rule-based. However, the complicated electromagnetic interaction between closely placed circuit patterns can not only induce additional optical proximity effect but also change the shadowing effect. These detailed phenomena cannot be completely taken into account by the rule-based approaches. A fully model-based approach, which integrates an in-house model-based optical proximity correction (OPC) algorithm with rigorous three-dimensional (3D) EUV mask simulation, is proposed to simultaneously compensate for shadowing and optical proximity effects with better pattern transfer fidelity and process windows. Preliminary results indicate that this fully model-based approach outperforms rule-based ones, in terms of geometric printability under process variations.

In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured and compared with simulation result to match the predictability of the simulation tool. Shadowing test comparison of wafer to simulation showed that simulation with resist model showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within 2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.

As the design node gets smaller, using the aggressive mask optimization becomes indispensable emerging technology. However, during the aggressive optimization, we have frequently met problems that the optimized feature size gets smaller as Mask manufacturing Rule Checking (MRC) limitation. In this case, process window cannot improve more. Moreover, mask drawing error could be significant when the optimized main feature is as small as MRC limitation. As a solution for this problem, we have generally tried to develop the advanced mask manufacturing process. However, nowadays, it is truly not easy to improve the mask resolution. In this study, we found out the fact that the current MRC parameters are not good enough to reflect the mask patterning limitation. Thus, many small patterns have been eliminated by the MRC during the optimization, even though the patterns could be drawn well on the mask. In this paper, we suggest more effective MRC parameter; area based MRC. We introduce the evaluation result that represents the actual coverage of MRC. It proves that the area based MRC can reflect the mask process limitation much better than current MRC. Finally it is shown that the effect and utility of the area based MRC on the practical case by using inverse lithography technology (ILT).

In this paper, we develop an image-gradient-based algorithm to simultaneously optimize various cost functions for inverse mask design. The algorithm employs an iterative approach which evaluates the gradient decent of the resist image, aerial image, and the aerial image contrast with a pre-assigned step length. Moreover, an independent iteration step is inserted among iterations for binary mask conversion. We show that the proposed algorithm allows fast convergence while achieving high aerial image contrast. The impacts of each cost function on the pattern fidelity and convergence are also discussed.

The Finite-Difference Time-Domain (FDTD) method is used to study the scattering effects of extreme ultraviolet (EUV) mask. It requires significant amounts of memory and computation time as the fine grid size is needed for simulation. Theoretically, the accuracy can be increased as the mesh size is decreased in FDTD simulation. However, it is not easy to get the accurate simulation results for the multilayer (ML) structures by FDTD method. The transmission line theory is used to calculate the equivalent refractive index for EUV mask ML to simulate the ML as one layer of bulk artificial material. The reflectivities for EUV light with the normal incidence and small-angle oblique incidence in the bulk artificial material and EUV mask ML are simulated by FDTD method. The Fresnel's equation is used to evaluate the numerical errors for these FDTD simulations, and the results show good agreement between them. Using the equivalent refractive index material for EUV multilayer mask can reduce the computation time and have the accuracy with tolerable numerical errors. The ML structure with periodic surface roughness is also studied by this method, and it shows that only half of computation time is needed to substitute ML to a bulk equivalent refractive index material in FDTD simulations. This proposed method can accelerate the simulations of EUV mask designs.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

This paper describes the principle and performance of a fully programmable illuminator for a high-NA immersion system. Sources can be generated on demand, by manipulating an array of mirrors instead of the traditional way of inserting optical elements and changing lens positions. All mirrors are always used to create the source such that no light is lost when switching from one source shape to another. Measured sources generated with this new type of illumination system will be shown and compared to the target sources generated by source mask optimization software or targets of traditional sources. Comparison between measured and target source will be done both in parameters of a pupil fit model and by simulated imaging impact. Also the first results in resist obtained on a XTIV 1950Hi 1.35 NA tool equipped with this illuminator are presented and compared to measurements on the same system when it was equipped with an Aerial XP illumination system.

Double patterning (DP), an extension of immersion, is the leading contender for the manufacturing of 32 nm half pitch node devices. For DP, substantial improvement in overlay accuracy is required to meet the CDU requirements for the 32 nm node, and substantial increase in throughput is required to meet the cost requirements. To meet these challenges, Nikon introduced the NSR-S620. The S620 is based on the Streamlign platform, which is characterized by three innovations: Bird's Eye Control, Stream Alignment, and Modular² Structure. In addition, many of the current systems and techniques have been refined to meet the requirements for DP. This presentation will discuss these technological improvements and show the latest technical results.

Double patterning is one of the main enabling technologies for expanding lithography beyond 45nm technology node. Geometric pitch split and litho friendly design is the core of double patterning. There has been lot of development recently in area of DP to minimize split errors and hot spots. In this paper we demonstrate one such application of predictive modeling to detect hot spots. The matrix for pitch splitting is developed at higher resolution wavelengths in design stage and the decomposed results are evaluated with different source types. This type of predictive model confronts hot spot information and un-resolvable pitches in design stage and assists in developing restricted design rules for litho friendly design.

It will be required for more accurate lithography simulation of complicated mask patterns then ever, under hyper-NA (numerical aperture) projection lens and aggressive small-aperture polarized-light illumination, to construct two systems of polarimetry; one is polarimetry for illumination, and the other is Mueller matrix polarimetry for projection lenses. The former polarimetry already reported by the authors is necessary for us to appreciate how the true polarization state of illumination is. The polarimeter mask described in the paper determines illumination polarization states by Stokes parameters. The latter polarimetry is the main subject of this paper. A Mueller matrix is a translation matrix of the input Stokes parameters to the output Stokes parameters. With the full elements of the Mueller matrix of a projection lens, the Stokes parameters of a light at the wafer plane can be easily predicted from the Stokes parameters of any illumination conditions. This paper proposed a new method of Mueller matrix polarimetry and a monitor mask used for 193-nm immersion lithography tools with a polarization monitor at the wafer plane.

The ability to extend deep ultraviolet (DUV) lithography into the 32 and sub-32nm domain has more recently relied on improvements in source-mask optimization (SMO), double patterning (DP) and complex, pixellated illumination patterns. Yet these techniques require a commensurate improvement in the light source that powers the latest generation scanners in order to enable high performance at high throughput. This paper will show detailed performance results of the latest-generation light source from Cymer that incorporates flexible power with dramatic improvements in dose, wavelength and bandwidth stability.

We obtained the acceptable mask defect size for both opaque and clear defects in the spacer patterning process using the fail-bit-map analysis and a mask with programmed defects. The spacer patterning process consists of the development of photoresist film, the etching of the core film using the photoresist pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the core film. The pattern pitch of the spacer film becomes half that of the photoresist. Both the opaque defect and the clear defect of the mask resulted in a short defect in the spacer pattern. From the fail-bit-map analysis, the acceptable mask defect size for opaque and clear defects was found to be 80nm and 120nm, respectively, which could be relaxed from that in ITRS2008. The difference of the acceptable mask defect size for opaque and clear defects comes from the difference of the defect printability at the resist development.

E-Reticle^™ system is an electrostatic field test device, which has the form factor of a conventional six inch quartz production reticle. The E-Reticle was used to assess the ESD damage risks in a mask cleaning tool. Test results indicate that a reticle may see higher than ITRS recommended electrostatic potential specifications when mechanical operations and cold DIW rinse start and in progress, hence seeing increased probability of electrostatic induced damages.

New lithography techniques like Double Patterning, Computational Lithography and Source Mask Optimization will be used to drive immersion lithography at 193nm to its limits. The photomask will become more and more a critical optical element in the scanner beam path. Precise image transfer of the circuit features into the resist will be key for the mask manufacture and its qualification. The extremely high MEEF values in low k1 lithography dramatically amplify small process variations on the mask features to the wafer print. Complex mask features using sophisticated OPC and assist features require mask metrology under scanner conditions which measured the optical performance of the mask. Double patterning technology tightens the registration and CDU specification of the patterns at the same time. Especially, overlay becomes more and more critical and must be ensured on every die. In-die registration and CD metrology on arbitrary features at scanner wavelength can measure the mask performance precisely and ensure correct print results and high yield in the wafer fab. Moreover even a complete set of phase shift measurements, CD and registration measurements in the die features can help to ensure that mask manufacture and its qualification provide indeed the largest process window for wafer printing. It is key for higher yield and better performance. In this paper an overview about several actinic in-die metrology techniques will be given. Focus will be on application of in-die CD measurements using the Zeiss WLCD tool as well as in-die registration measurements using the Zeiss Prove tool will be shown and discussed.

High transmission attenuated phase shift masks (Hi-T PSM) have been successfully applied in volume manufacturing for certain memory devices. Moreover, numerous studies have shown the potential benefits of Hi-T PSM for specific lithography applications. In this paper, the potential for extending Hi-T PSM to logic devices, is revisited with an emphasis on understanding layout, transmission, and manufacturing of Hi-T PSM versus traditional 6% embedded attenuated phase shift mask (EAPSM). Simulations on various layouts show Hi-T PSM has advantage over EAPSM in low duty cycle line patterns and high duty cycle space patterns. The overall process window can be enhanced when Hi- T PSM is combined with optimized optical proximity correction (OPC), sub-resolution assist features (SRAF), and source illumination. Therefore, Hi-T PSM may be a viable and lower cost alternative to other complex resolution enhancement technology (RET) approaches. Aerial image measurement system (AIMS) results on test masks, based on an inverse lithography technology (ILT) generated layout, confirm the simulation results. New advancement in high transmission blanks also make low topography Hi-T PSM a reality, which can minimize scattering effects in high NA lithography.

Back (glass) side haze on photomasks has been previously reported and continues to present problems in many fabs throughout the industry. While some process changes have resulted in the reduction in both the occurrences and rate at which back side haze forms; proper handling and storage of reticles remains paramount in protecting all surfaces on the reticle from haze formation. We will describe again the basic mechanisms for haze formation and how proper storage can result in significantly reducing the risk of haze formation during storage and use in the fab.

Recently pattern overlay accuracy becomes more important because of the small pitch patterning. Immersion technology enabled usage of hyper NA beyond 1.0 and this technology provided a lot of possibility to make a very small patterns. But there was no significant technical jump for overlay. Therefore chip makers started to compensate non-linear systematic overlay errors. For example, high order inter-field overlay correction is used to improve overlay performance between the tool to tool matching. Now chip makers are planning to compensate in-shot(intra-field) overlay with higher order compensation than before. Scanner vendors provide intra-field matching options such as i-HOPC(intra-field high order process correction - ASML) and SDM (Super Distortion Matching - Nikon). Those are the methods to match inshot overlay easily. However there are a lot of arguments what the correct way is to measure the in-shot overlay and how we can feedback those measured data to APC system. Especially for the distortion measurement of scanner, we have different data from the mass production trend of distortion. The pattern dependency and another cause of in-shot (intra-field) overlay error will be defined. This will provide a clue to solve difference between the mass production in-shot overlay trend and machine distortion data. The final goal of this study is providing a small hint to design APC system controlling the in-shot(intra-field) overlay with less overlay error.

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level [4]. Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform. This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus) and product wafer applications.

Scatterometry has been used extensively for the characterization of critical dimensions (CD) and detailed sidewall profiles of periodic structures in microelectronics fabrication processes. So far the majority of applications are for symmetric gratings. In most cases devices are designed to be symmetric although errors could occur during fabrication process and result in undesired asymmetry. The problem with conventional optical scatterometry techniques lies in the lack of capability to distinguish between left and right asymmetries. In this work we investigate the possibility of measuring grating asymmetry using Mueller matrix spectroscopic ellipsometry (MM-SE). A patterned hard disk prepared by nano-imprint technique is used for the study. The relief image on the disk sometimes has asymmetrical sidewall profile, presumably due to the uneven separation of the template from the disk. The undesired tilting resist profile causes difficulties to the downstream processes or even makes them fail. Cross-section SEM reveals that the asymmetrical resist lines are typically tilted towards the outer diameter direction. The simulation and experimental data show that certain Mueller matrix elements are proportional to the direction and amplitude of profile asymmetry, providing a direct indication to the sidewall tilting. The tilting parameter can be extracted using rigorous optical critical dimension (OCD) modeling or calibration method. We demonstrate that this technique has good sensitivity for measuring and distinguishing left and right asymmetry caused by sidewall tilting, and can therefore be used for monitoring processes, such as lithography and etch processing, for which symmetric structures are desired.

As electronic users demand smaller form factor of devices that can pack more functionality, Semiconductor industry has been marching towards smaller design rules. With the advancement in newer design nodes such as 32nm and beyond, additional challenges are being faced by the Fabs developing the process technologies. These challenges are often difficult to solve using traditional approaches and therefore novel techniques must be implemented to address the challenges accordingly. In the area of wafer inspection, the traditional approach of simply using wafer level data alone is no longer sufficient. Some specific challenges regarding systematic defects that the Fabs are facing today are discussed in this paper along with several approaches that can help meet the challenges. These new approaches can help to take the wafer inspection to the next level in order to detect and identify key yield deterrents that limit reaching yield entitlement in a timely manner.

Readiness of defect-free mask is one of the biggest challenges to insert extreme ultraviolet (EUV) lithography into semiconductor high volume manufacturing for 22nm half pitch (HP) node and beyond. According to ITRS roadmap updated in 2008, minimum size of defect needed to be removed is 25nm for 22nm HP node in 2013 [1]. It is necessary, therefore, to develop EUV mask pattern inspection tool being capable of detecting 25nm defect. Electron beam inspection (EBI) is one of promising tools which will be able to meet such a tight defect requirement. In this paper, we evaluated defect detection sensitivity of electron beam inspection (EBI) system developed by Hermes Microvision, Inc. (HMI) using 88nm half-pitch (HP) line-and-space (L/S) pattern and 128nm HP contact-hole (C/H) pattern EUV mask. We found the EBI system can detect 25nm defects. We, furthermore, fabricated 4 types of EUV mask structures: 1) w/ anti-reflective (AR) layer and w/ buffer layer, 2) w/ AR layer and w/o buffer layer, 3) w/o AR layer and w/ buffer layer, 4) w/o AR layer and w/o buffer layer. And the sensitivity and inspectability for the EBI were compared. It was observed that w/o AR layer structure introduce higher image contrast and lead to better inspectability, although there is no significant different in sensitivity.

In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.

Materials and processes for double patterning using 193nm immersion lithography has been developed for the 32/22 nm node device generations. As for double patterning , some patterning methods have already been reported. For instance, there are LELE (Litho Etch Litho Etch) process and LFLE (Litho Freeze Litho Etch) process. LELE process is complicate and low throughput compared to LFLE process. On the other hand, freezing process and freezing material are needed in LFLE process. Then, we examined the process and the material that was able to form a minute pattern without increasing the number of processes as much as possible. The following is examined as a fine hole patterning process. At first, the pillar pattern is obtained by the X-Y double line dipole exposure. Secondly, the reverse material is applied on the pillar pattern and the subsequent process (dry etching or wet etching process) converts the pillar pattern into a hole pattern. We examined the reverse process and materials, including Silicon Glass for Etch Reverse Layer (SiGERL),and organic Bottom-Anti-Reflective coating (BARC) which is adequate for reflectivity control, lithography and the etching process.

The CD control of the first lithography (L1) patterns is a important issue in the single-etch double patterning (SEDP) process. In this process, L1 patterns are cured either chemically or thermally and then subjected to the second lithography (L2). A chemical curing process using a surface curing agent (SCA) often results in the CD growth due to the "positive" interaction between the first and second resists. A thermal curing process using a thermal cure resist (TCR) often results in the CD loss due to the volumetric shrinkage of the L1 patterns during the L2 process. By combining SCA and TCR concepts, we developed a simple "hybrid" curing system which offers precise control of the L1 CD after double patterning. This hybrid curing system involves thermal curing followed by a liquid rinse process using a double patterning primer (DPP). DPP is an aqueous solution formulated with SCA components and enhances "positive" interaction between L1 and L2 patterns. While CD loss of 5~6nm is observed without DPP treatment, ~11nm CD growth was observed with TCR after DPP treatment. The L1 CD after double patterning was precisely controllable by post-priming bake process with the rate of -0.3nm/°C in the temperature ranging from 120 ~ 150°C. Taking advantage of the CD growth with DPP treatment, we further developed three different advanced patterning schemes: 1. "Shrink Process Assisted by Double Exposure" (SPADE I), 2. "Space Patterning Assisted by Double Exposure" (SPADE II), and 3. "Sidewall Patterning Assisted by Double Exposure" (SPADE III). Using SPADE I, contact hole CD was reduced by 10~30nm and excellent through pitch performance was observed. SPADE I can also improve LER/LWR when used in the formation of smaller trenches. SPADE II was developed for self-aligned pitch splitting of contact holes and SPADE III was developed for self-aligned pitch splitting of lines. In this paper, the use of DPP in various SPADE technologies is described and its potential in the advanced patterning schemes is discussed.

The SOKUDO DUO track system incorporates a dual-path wafer flow to reduce the burden on the wafer handling unit and enables high-throughput coat/develop/bake processing in-line with semiconductor photolithography exposure (scanner) equipment. Various photolithography-based double patterning process flows were modeled on the SOKUDO DUO system and it was confirmed to be able to process both Litho-Process-Litho-Etch (LPLE)*² and negative-tone develop process wafers at greater than 200 wafer-per-hour (wph) capability for each litho-pass through the in-line exposure tool. In addition, it is demonstrated that Biased Hot Plates (BHP) with "cdTune" software improves litho pattern #1 and litho pattern #2 within wafer CD uniformity. Based primarily on JSR Micro materials for Litho-Freeze- Litho-Etch (LFLE) the coat, develop and bake process CD uniformity improvement results are demonstrated on the SOKUDO RF3S immersion track in-line with ASML XT:1900Gi system at IMEC, Belgium.

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Filtration products utilizing Nylon 6,6 membrane technology have demonstrated effectiveness in reducing microbridge defects in DUV photoresist patterning. The effects of fluid flow characteristics on defect reduction using a point-of-use Nylon 6,6 filtration product are explored. Lower filtration pressure and longer contact time were found to enhance the removal of gel-like microbridge defect precursors during point-of-use filtration of photoresist polymer solution. A kinetic study of high-pressure filtration, where a strong dependency of gel removal on contact time is observed, revealed the gel-like precursors are adsorbed to a greater extent at sites of polar Nylon 6,6 throughout the membrane depth. A study of gel capturing position by ICP-MS for low-pressure filtration, where gel removal is independent of contact time, revealed the gels are captured at the inlet portion of the filter, due to smaller transportation force, as compared to deeper into the filter media depth. These findings will be very useful both in optimizing filter operating procedures and in the development of next-generation filtration products, ultimately contributing toward reduced defectivity and increased yield within next-generation lithography processes.

Extreme ultra-violet (EUV) lithography technology is being developed for the patterning of sub-22nm node. Line edge roughness (LER) is the one of the important issues together with the resist performance like resolution and sensitivity. There are some novel resists for EUV lithography that can be used for obtaining the target resolution and sensitivity, while the line edge roughness do not reached the target values in most resist yet. In order to reduce the LER, the molecular resist has been widely studied due to their small size compared to the conventional polymer resist. There is another approach to reduce the LER by reducing the acid diffusion length, but it is not easy to reduce down the acid diffusion length. We tried a new approach to reduce down the LER by changing the shape or structure of the molecular resist. A new molecular resist shape that shows the anisotropic structure is tried to see the LER and whether this anisotropic resist can be used for LER reduction. It turns out that the LER is minimum when the molecular chain alignment is along the depth, while LER is maximum when the molecular chain is randomly distributed.

During the chip making process, complete removal of photo-resist is very critical. Current metrology & analytical methods do not provide enough sensitivity to detect residual amounts of photo-resist remaining on the wafer. Using the novel method described in this study, the Surfscan SP2 and SURFmonitor solution has successfully demonstrated the sensitivity needed to detect residual photo-resist. This method takes advantage of the fact that residual photo-resist, which is organic in nature, will fluoresce. By scanning wafers after the ash and clean step using the SP2 (UV wavelength) unpatterned defect inspection tool equipped with SURFmonitor, it is possible to generate a full-wafer fluorescence SURFimage. This SURFimage was shown to clearly indicate the regions of the wafer where residual photoresist was present.

A newly developed stochastic resist model, implemented in a prototype version of the PROLITH lithography simulation software is fitted to experimental data for a commercially available immersion ArF photoresist, EPIC 2013 (Dow Electronic Materials). Calibration is performed only considering the mean CD value through focus and dose for three line/space features of varying pitch (dense, semi-dense and isolated). An unweighted Root Mean Squared Error (RMSE) of approximately 2.0 nm is observed when the calibrated model is compared to the experimental data. Although the model is calibrated only to mean CD values, it is able to accurately predict LER through focus to better than 1.5 nm RMSE and highly accurate CDU distributions at fixed focus and dose conditions. It is also shown how a stochastic model can be used to the describe the bridging behavior often observed at marginal focus and exposure conditions.

LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization when design is not manufacturable with DPT and mask assignment either when it is or despite it is not. Concurrent with the advancements in double patterning process, there has been active research [1] [2] [3] [4] addressing the problem of mask planning. As geometries across the chip can potentially involve in the same conflict, DPT decomposition has been recognized as unbounded [5] [4]. We will show in this paper that the unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of fully flattened design are even more amenable in that they are already positioned with respect to the flat view, and tiles overlap only marginally when they do. While there have been ample research literature in the mask assignment problem with respect to geometries within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special handling needed for peculiar complexities arising from the presence of hierarchy [5] [6]. Hierarchy adds a subtle but significant dimension to the mask planning problems. This paper investigates contact layer mask planning for DPT, and presents results on two new problems due to hierarchical processing.