12 December 2009 Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods
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Proceedings Volume 7520, Lithography Asia 2009; 75200X (2009); doi: 10.1117/12.843578
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
Abstract
For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.
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Linyong Pang, Peter Hu, Danping Peng, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason, "Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods", Proc. SPIE 7520, Lithography Asia 2009, 75200X (12 December 2009); doi: 10.1117/12.843578; https://doi.org/10.1117/12.843578
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KEYWORDS
Source mask optimization

Photomasks

SRAF

Lithography

Optical proximity correction

Photovoltaics

Logic

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