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11 December 2009 Systematic defect management by design aware inspection
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Proceedings Volume 7520, Lithography Asia 2009; 75201C (2009)
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
As electronic users demand smaller form factor of devices that can pack more functionality, Semiconductor industry has been marching towards smaller design rules. With the advancement in newer design nodes such as 32nm and beyond, additional challenges are being faced by the Fabs developing the process technologies. These challenges are often difficult to solve using traditional approaches and therefore novel techniques must be implemented to address the challenges accordingly. In the area of wafer inspection, the traditional approach of simply using wafer level data alone is no longer sufficient. Some specific challenges regarding systematic defects that the Fabs are facing today are discussed in this paper along with several approaches that can help meet the challenges. These new approaches can help to take the wafer inspection to the next level in order to detect and identify key yield deterrents that limit reaching yield entitlement in a timely manner.
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Ellis Chang and Allen Park "Systematic defect management by design aware inspection", Proc. SPIE 7520, Lithography Asia 2009, 75201C (11 December 2009);

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