Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The
major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window
Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is
normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands
of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review
and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly
and if they can be classified into groups, it would be possible to save a lot of time for the analysis.
We have demonstrated an EDA tool which can handle the large amount of output data from DBM by classifying
pattern defects into groups. It can classify millions of patterns into less than thousands of pattern groups. It has been
evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns
in a DRAM device. Also, verification was tuned to specific needs of the designer as well as defect analysis
engineers by use of EDA tool's 'Pattern Matching Function'. The verification result was well within the required
specification of the designer as well as the analysis engineer. The procedures of Hot Spot Management through
Design Based Metrology are presented in detail.