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12 December 2009 Control of CD errors and hotspots by using a design based verification system
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Proceedings Volume 7520, Lithography Asia 2009; 75201X (2009)
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
The shrink of device node to raise the integration is important for the raising of cost performance on memory device. Targeting the feature critical dimension (CD) and defect control to achieve a large process margin and high product yield become an essential management point under the node shrink, thus sufficient works have been progressed on the product level. In the immersion lithography, the performance of CD and defect control range is intensively improved because of high equipment performances. However, proximity effect causes the CD variation and unknown hotspots because of environmental variation. In this work, control of the CD errors and hotspots will be discussed by using a verification system with an image verifier algorithm between design layout and wafer images. We used NGR2100TM as a verification system. The verification works for the CD distributions and hotspot detection are implemented on sub 50 nm node memory device. In the experiment, improved CD distributions were examined based on retarget correction for CD errors and the controllability of hotspots are explained from the examined methodology.
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Bong-Seok Choi, Sang-Ho Lee, Young-Seog Kang, and Woo-Sung Han "Control of CD errors and hotspots by using a design based verification system", Proc. SPIE 7520, Lithography Asia 2009, 75201X (12 December 2009);

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