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14 December 2009 Heat conduction from hot plate to photoresist on top of wafer including heat loss to the environment
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Proceedings Volume 7520, Lithography Asia 2009; 75202I (2009)
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
Post exposure bake (PEB) process among the lithography steps is important for making good patterns when the chemically amplified resist is used. During the PEB, the de-protection reaction and the acid diffusion are determined by bake temperature and time. One of the key factors that determine the de-protection and acid diffusion is the initial temperature rising inside the photoresist. The time delay due to the temperature rising from the room temperature to the pre-set bake temperature is the main cause of line width variation. It is very important to control 1~2 nm line width variation for patterns of 32 nm and below. This variation mainly comes from PEB temperature and time of the resist on top of the multi-stacking silicon wafer on hot plate. In order to predict the accurate PEB temperature and time applied to the resist, we studied heat transfer from hot plate to the resist on top of the silicon wafer. We calculated boundary temperature values of each layer and compared the change of temperature caused by different kinds and thicknesses of sublayers including antireflection coating and resist. In order to predict bake temperature, we have to consider the heat loss which was made by the temperature differences with surrounding air, conductivity difference of various layer, and nitrogen purge during the PEB process. Therefore, heat loss to the environment is included to solve real heat conduction problem in the hot plate of the track system. We also found that the resultant line width was changed by small temperature variation, stack thickness and layer numbers.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Minhee Jung, Sarah Kim, Do Wan Kim, and Hye-Keun Oh "Heat conduction from hot plate to photoresist on top of wafer including heat loss to the environment", Proc. SPIE 7520, Lithography Asia 2009, 75202I (14 December 2009);

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