Radiation-hardening-by-design with circuit-level modeling of total ionizing dose effects in modern CMOS technologies

M. S. Gorbunov; G. I. Zebrev; P. N. Osipenko

doi:10.1117/12.853580

26 February 2010 Radiation-hardening-by-design with circuit-level modeling of total ionizing dose effects in modern CMOS technologies

M. S. Gorbunov, G. I. Zebrev, P. N. Osipenko

Author Affiliations +

Proceedings Volume 7521, International Conference on Micro- and Nano-Electronics 2009; 75211F (2010) https://doi.org/10.1117/12.853580
Event: International Conference on Micro- and Nano-Electronics 2009, 2009, Zvenigorod, Russian Federation

Abstract

Physical model of total ionizing dose (TID) effects previously developed and successfully verified by authors was embedded to BSIM3v3 model implemented using Verilog-A language. This tool is fully compatible with standard SPICE simulators and allows taking into account the electrical bias conditions for each transistor during irradiation.

Citation Download Citation

M. S. Gorbunov, G. I. Zebrev, and P. N. Osipenko "Radiation-hardening-by-design with circuit-level modeling of total ionizing dose effects in modern CMOS technologies", Proc. SPIE 7521, International Conference on Micro- and Nano-Electronics 2009, 75211F (26 February 2010); https://doi.org/10.1117/12.853580

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