18 January 2010 Hot pixel reduction in CMOS image sensor pixels
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Abstract
Reducing hot pixels is a challenge commonly faced in the image sensor industry and there are various techniques used to address this problem, including image processing and process optimization. This paper discusses an approach to reduce hot pixels by using Technology Computer Aided Design (TCAD) simulations to optimize the pixel at the process level. A correlation between empirical hot pixel data and simulated electric field is discussed. For this given process, there is good correlation between hot pixel count and the electric field along the top p-n junction of the photodiode. By optimizing the top p-n junction, we were able to reduce the hot pixel count to less than 100ppm at 45C for a threshold value of 15% of full scale. However, careful consideration must be made during the process optimization. When photodiode implant doses and energies are changed, image lag performance can deteriorate. Changing photodiode implant doses and energies can also result in n-type penetration through the polysilicon gate, which can lead to increased dark current. A careful design will avoid such problems. During our process optimization, we successfully reduced hot pixel count while still achieving low dark current. These achievements can be observed in dark current of less than 3 e- /sec-pixel at 45C.
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Jonathan Yu, David J. Collins, Alireza Yasan, Sanghoon Bae, Shri Ramaswami, "Hot pixel reduction in CMOS image sensor pixels", Proc. SPIE 7537, Digital Photography VI, 753704 (18 January 2010); doi: 10.1117/12.839118; https://doi.org/10.1117/12.839118
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