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4 February 2010 Wafer-level vacuum/hermetic packaging technologies for MEMS
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Abstract
An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.
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Sang-Hyun Lee, Jay Mitchell, Warren Welch, Sangwoo Lee, and Khalil Najafi "Wafer-level vacuum/hermetic packaging technologies for MEMS", Proc. SPIE 7592, Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS and Nanodevices IX, 759205 (4 February 2010); doi: 10.1117/12.843831; https://doi.org/10.1117/12.843831
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