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16 February 2010 New interpretation of photonic yield processes (450-750nm) in multi-junction Si CMOS LEDs: simulation and analyses
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Proceedings Volume 7606, Silicon Photonics V; 760613 (2010) https://doi.org/10.1117/12.843134
Event: SPIE OPTO, 2010, San Francisco, California, United States
Abstract
Emission levels in the 450-750nm range of about 80-100 fold higher than that emitted by single junction avalanche LEDs, has been obtained. CMOS Si LED p+-i-np+ structures were modeled in order to investigate the effect of various depletion layer profiles and defect engineering on the photonic transitions in the 1.4 to 2.8 eV, 450-750nnm regime. Modeling and device simulation results showed that by utilizing a short lowly doped layer in between a highly doped p+ layer and n layer can enhance the photonic yields by orders of magnitude through an increase in the dynamic carrier densities in the device and favoring enhanced lateral multiplication processes. The electric field profile should be of the order of 5 x 105 V.cm-1 and about 0.5 micron long. Injecting of carriers of opposite charge type from an opposing forward bias junction further enhance the photonic yield. These models and interpretations is confirmed by analyses of device designs as realized in 1.2 μm and 0.35 CMOS technology. The device design involved normal CMOS design and processing procedures with no excessive micro-dimensioning. The current devices operated in the 8-10V, 1uA - 2mA regime and yield emission intensities of up to 100 nW.μm-2. The current emission levels are about three orders higher than the low frequency detectability limit of Si CMOS p-n detectors of corresponding area. The particular design favors higher emission levels towards the 750nm wavelength region. This makes diverse electro-optical applications possible such as optical communication on chip, diverse optical signal processing and wave-guiding. It also enables realization of on chip Micro-Optical-Electro-Mechanical Sensors (MOEMS), which could lead to the development of so-called "smart chips" utilizing standard CMOS integrated circuitry.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lukas W. Snyman and Enrico Bellotti "New interpretation of photonic yield processes (450-750nm) in multi-junction Si CMOS LEDs: simulation and analyses", Proc. SPIE 7606, Silicon Photonics V, 760613 (16 February 2010); https://doi.org/10.1117/12.843134
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