23 February 2010 Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link
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Abstract
An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.
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Jamshid Sangirov, Jamshid Sangirov, Nga T. H. Nguyen, Nga T. H. Nguyen, Trong-Hieu Ngo, Trong-Hieu Ngo, Dong-min Im, Dong-min Im, Augustine I. Ukaegbu, Augustine I. Ukaegbu, Tae-Woo Lee, Tae-Woo Lee, Mu Hee Cho, Mu Hee Cho, Hyo-Hoon Park, Hyo-Hoon Park, } "Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link", Proc. SPIE 7607, Optoelectronic Interconnects and Component Integration IX, 76071B (23 February 2010); doi: 10.1117/12.843063; https://doi.org/10.1117/12.843063
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