19 November 2009 Performance evaluation for optical network-on-chip interconnect architectures
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Proceedings Volume 7633, Network Architectures, Management, and Applications VII; 76330S (2009) https://doi.org/10.1117/12.852107
Event: Asia Communications and Photonics, 2009, Shanghai, Shanghai , China
A large number of IP cores will be included in the future systems-on-chip (SoC). Traditional bus-based architectures are no longer suitable for modern chip design, since it is difficult to expand, consumes much power and takes much area. Network-on-chip (NoC), which employs networks to replace buses as a scalable global communication platform, has been proposed to cope with these problems. However, limited bandwidth, long delay and high power consumption will become bottlenecks as NoC scales to large sizes. Based on silicon optical interconnect, optical network-on-chip (ONoC) can offer significant bandwidth and power advantages, which provides a promising solution to overcome these limitations. In this paper, we simulated and compared several ONoCs based on the topologies including 2D Mesh, 3D Mesh, 2D Fat Tree(FT) and 2D Butterfly Fat Tree(BFT) in terms of the end-to-end delay and network throughput. The results showed that 3D Mesh has the best performance among the listed topologies.
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Shiqing Wang, Shiqing Wang, Huaxi Gu, Huaxi Gu, } "Performance evaluation for optical network-on-chip interconnect architectures", Proc. SPIE 7633, Network Architectures, Management, and Applications VII, 76330S (19 November 2009); doi: 10.1117/12.852107; https://doi.org/10.1117/12.852107


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