Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Hajime Aoyama; Yuusuke Tanaka; Kazuo Tawarayama; Naofumi Nakamura; Eiichi Soda; Noriaki Oda; Yukiyasu Arisawa; Taiga Uno; Takashi Kamo; Kentaro Matsunaga; Daisuke Kawamura; Toshihiko Tanaka; Hiroyuki Tanaka; Shuichi Saito; Ichiro Mori

doi:10.1117/12.846325

22 March 2010 Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Hajime Aoyama, Yuusuke Tanaka, Kazuo Tawarayama, Naofumi Nakamura, Eiichi Soda, Noriaki Oda, Yukiyasu Arisawa, Taiga Uno, Takashi Kamo, Kentaro Matsunaga, Daisuke Kawamura, Toshihiko Tanaka, Hiroyuki Tanaka, Shuichi Saito, Ichiro Mori

Author Affiliations +

Proceedings Volume 7636, Extreme Ultraviolet (EUV) Lithography; 76361N (2010) https://doi.org/10.1117/12.846325
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Citation Download Citation

Hajime Aoyama, Yuusuke Tanaka, Kazuo Tawarayama, Naofumi Nakamura, Eiichi Soda, Noriaki Oda, Yukiyasu Arisawa, Taiga Uno, Takashi Kamo, Kentaro Matsunaga, Daisuke Kawamura, Toshihiko Tanaka, Hiroyuki Tanaka, Shuichi Saito, and Ichiro Mori "Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76361N (22 March 2010); https://doi.org/10.1117/12.846325

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available