22 March 2010 Process liability evaluation for beyond 22nm node using EUVL
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Abstract
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kazuo Tawarayama, Hajime Aoyama, Kentaro Matsunaga, Yukiyasu Arisawa, Taiga Uno, Shunko Magoshi, Suigen Kyoh, Yumi Nakajima, Ryoichi Inanami, Satoshi Tanaka, Ayumi Kobiki, Yukiko Kikuchi, Daisuke Kawamura, Kosuke Takai, Koji Murano, Yumi Hayashi, Ichiro Mori, "Process liability evaluation for beyond 22nm node using EUVL", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76361O (22 March 2010); doi: 10.1117/12.846265; https://doi.org/10.1117/12.846265
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