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22 March 2010 Practical flare compensation strategy for DRAM device
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Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real device is measured experimentally with real device layout with clearing pads in it. Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.
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Chang-Moon Lim, Jun-Taek Park, James Moon, Sunyoung Koo, Yoonsuk Hyun, Hyeong Soo Kim, Donggyu Yim, and Sung-Ki Park "Practical flare compensation strategy for DRAM device", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76362B (22 March 2010);

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