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22 March 2010 Further investigation of EUV process sensitivities for wafer track processing
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As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Neil Bradon, K. Nafus, H. Shite, J. Kitano, H. Kosugi, M. Goethals, S. Cheng, J. Hermans, E. Hendrickx, B. Baudemprez, and D. Van Den Heuvel "Further investigation of EUV process sensitivities for wafer track processing", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 763630 (22 March 2010);

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