In this paper, the status of mask-less lithography for advanced semiconductor applications is reviewed. Mask-less
lithography received a lot of interest as the lithography for manufacturing the critical layers of advanced integrated
processes, because of the severe increase in mask costs that the industry is experiencing for critical layers as of the
45nm technology onwards. The availability of mask-less lithography would allow to get rid of these mask costs,
which is in particular interesting for low volume products.
First the various mask-less initiatives are reviewed, with emphasis on the European ones. The typical results that
are obtained by these groups are reviewed and compared to the requirements that need to be met to become the
lithography process of choice for the manufacturing of certain critical layers in advanced chips. The requirements
are typically expressed in terms of resolution, overlay and throughput.
A number of key conclusions are drawn : focus of mask-less tool development should be on insertion at the 16nm node, with extendibility to 11nm. Promising resolution results have been demonstrated by various groups. Today the proof-of-concept tools have not shown any overlay nor throughput performance, which needs to become the main focus for the next few years. Finally, it is recommended to focus on a parallel beam mask writer initially, where the level of complexity is much lower but most of the same challenges will need to be addressed.