This PDF file contains the front matter associated with SPIE Proceedings Volume 7638, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

With the continuous shrinkage of feature dimensions on IC in the semiconductor industry, the measurement uncertainty is becoming one of the major components that have to be controlled in order to guarantee sufficient production yield. Already at the R&D level, we have to cope up with the accurate measurements of sub-40nm dense trenches and contact holes coming from 193 immersion lithography or E-Beam lithography. By using top-down CD-SEM it is currently impossible to extract profile information. Moreover, electron proximity effect leads to non-negligible CD bias in the final measurements. To enable measurement of challenging dimensions with better measurement and reduced measurement uncertainty we have explored and fine tuned an alternative 3D-AFM mode (so-called DT mode) for CD measurements purpose. Theoretically, this mode is supposed to be dedicated only for height measurement but for certain applications it could be extended to reach the nanometer scale accuracy of CD-measurements employing certain optimized scan parameters. In this paper, we will present and discuss results obtained related to the use of this particular mode for CD measurement purpose versus conventional 3D-AFM CD Mode that shows important limitations for aggressive trenches dimensions measurements. We will also present some results related to the use of advanced 3D-AFM tips (typically of 28nm diameter) that have been used with the enhanced DT mode parameters. Example of applications will be shown with typical sub-45nm trenches measurements dedicated to advanced lithography process development that will demonstrate that we have succeed to push ahead the limit of the 3D-AFM technology in measuring the tight dimensions that would allow to continue its use for current and upcoming technology nodes. Finally, we introduce the concept of hybrid metrology in order to smartly use the benefit of reference metrology (i.e 3D-AFM) through the optimization of CD-SEM algorithm that could be used for example for OPC model optimization.

In this paper we demonstrate the robustness of the Mueller matrix polarimetry used in multiple-azimuth configuration. We first demonstrate the efficiency of the method for the characterization of small pitch gratings filling 250 μm wide square boxes. We used a Mueller matrix polarimeter directly installed in the clean room has motorized rotating stage allowing the access to arbitrary conical grating configurations. The projected beam spot size could be reduced to 60x25 μm, but for the measurements reported here this size was 100x100 μm. The optimal values of parameters of a trapezoidal profile model, acquired for each azimuthal angle separately using a non-linear least-square minimization algorithm, are shown for a typical grating. Further statistical analysis of the azimuth-dependent dimensional parameters provided realistic estimates of the confidence interval giving direct information about the accuracy of the results. The mean values and the standard deviations were calculated for 21 different grating boxes featuring in total 399 measured spectra and fits. The results for all boxes are summarized in a table which compares the optical method to the 3D-AFM. The essential conclusion of our work is that the 3D-AFM values always fall into the confidence intervals provided by the optical method, which means that we have successfully estimated the accuracy of our results without using direct comparison with another, non-optical, method. Moreover, this approach may provide a way to improve the accuracy of grating profile modeling by minimizing the standard deviations evaluated from multiple-azimuths results.

Advanced 193 nm lithographic processes will require defocus control for product wafers in order to meet CD and profile requirements in the future. Dose control is already required. The interaction of product wafer materials with lithography requires additional controls beyond tool monitoring. While scatterometry has demonstrated excellent ability to extract effective defocus and dose information from monitor wafers, the addition of product film stacks introduces several issues for this technique. The additional complexity of model generation and the sensitivity to under-layer thickness and optical property variation are among these. A CDSEM technique for lithography focus monitoring overcomes these issues provided it has sufficient precision and relative accuracy. In this paper, we report on comparative studies of two CDSEM techniques. One technique uses angled e-beam to better view the sidewall for edge width measurement. The angle of the beam from normal incidence is considerably larger than previously explored thereby enabling sensitive measurements on shallower structures. The other technique introduces new target designs particularly suited to CDSEM measurement that have enhanced sensitivity to focus and dose. Implementation of these techniques requires expanded sampling during the course of a single measurement in order to suppress roughness. The small target size of these structures enables applications with targets in product kerf and embedded within the circuit. In summary, these methods enable the measurement of dose and focus variations on product wafers.

As optical lithography pushes towards the 32nm node and as the k₁ factor moves toward 0.25, scanner performance and operational stability are the key enablers to meet device scaling requirements. Achieving these requirements in production requires stable lithography tools and processes. Stable performance is tracked with respect to pattern to pattern overlay, nominal focus and critical dimension uniformity (CDU). Within our paper we will characterize the intrinsic lithographic performance of the scanner and will discuss a new method of machine control to improve the stability and thus the overall performance of the lithographic solution. This is achieved by measuring specific monitor wafers, modeling the results by a new software algorithm and constantly feeding back corrective terms to the scanner. Diffraction-based optical dimensional scatterometry was selected because of its precision, its ability to measure overlay and focus with a single metrology recipe and its capability to generate greater amounts of measurement data in a shorter time period than other metrology techniques and platforms. While monitor wafer performance can be indicative, we will discuss the impact of the new control loop on product. We will take a closer look at possible interactions with the existing process control loops and work through the configuration of both internal and fab control loops. We will show improvements in the focus performance on product wafers by using scatterometry as well. Most importantly we will demonstrate that the newly implemented control loop resulted in a significant improvement of the CD and overlay performance of critical product layers. This had a very positive impact on overall process variation and the rework rate at lithography.

We have developed the new technology to measure focus variations in a field or over the wafer quickly for exposure tool management. With the new technology, 2-dimensional image(s) of the whole wafer are captured with diffraction optics, and by analyzing the image signal(s), we are able to get a focus map in an exposure field or over the entire wafer. Diffraction-focus curve is used instead of a CD-focus curve to get the focus value from the image signal(s). The measurements on the production patterns with the production illumination conditions are available. We can measure the field inclination and curvature from the focus map. The performance of the new method was confirmed with a test pattern and production patterns.

A powerful new inspection technology enables the excursion control of fast patterning processes. Full images of 300mm wafers are captured and processed to extract CD uniformity information of contact hole and line-space patterns. Suitable masking filters are applied to process and analyze the information from active logic and/or memory areas separately. Characteristic process tool signatures can then be detected based on die, exposure field and wafer-level pattern variations. Based on inspection times of a few seconds per wafer, rapid monitoring of 100% of processed wafers at full surface is feasible. CD-imaging is demonstrated for the monitoring of key patterning process steps in gate formation. Use cases for stand-alone, integrated and smart sampling strategies are discussed.

As critical dimension (CD) control requirements increase and process windows decrease, it is now of even higher importance to be able to determine and separate the sources of CD error in an immersion cluster, in order to correct for them. It has already been reported that the CD error contributors can be attributed to two primary lithographic parameters: effective dose and focus. In this paper, we demonstrate a method to extract effective dose and focus, based on diffraction based optical metrology (scatterometry). A physical model is used to describe the CD variations of a target with controlled focus and dose offsets. This calibrated model enables the extraction of effective dose and focus fingerprints across wafer and across scanner exposure field. We will show how to optimize the target design and the process conditions, in order to achieve an accurate and precise de-convolution over a larger range of focus and dose than the expected variation of the cluster. This technique is implemented on an ASML XT:1900Gi scanner interfaced with a Sokudo RF^3S track. The systematic focus and dose fingerprints obtained by this de-convolution technique enable identification of the specific contributions of the track, scanner and reticle. Finally, specific corrections are applied to compensate for these systematic CD variations and a significant improvement in CD uniformity is demonstrated.

Numerous metrology tools, techniques and methods are used by the industry to setup and qualify exposure tools for production. Traditionally, different metrology techniques and tools have been used to setup dose, focus and overlay optimally and they do so independently. The methods used can be cumbersome, have the potential to interfere with each other and some even require an unacceptable amount of costly exposure tool time for data acquisition. In this work, we present a method that uses an advanced angle-resolved scatterometry metrology tool that has the capability to measure both CD and overlay. By using a technique to de-convolve dose and focus based on the profile measurement of a well characterized process monitor target, we show that the dose and focus signature of a high NA 193nm immersion scanner can be effectively measured and corrected. A similar approach was also taken to address overlay errors using the diffraction based overlay capability of our metrology tool. We demonstrate the advantage of having a single metrology tool solution, which enables us to reduce dose, focus and overlay signatures to a minimum.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD corrections using Dose Mapper^TM. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose Mapper^TM dose recipe created before the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper.

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVision^TM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

For many critical lithography applications the main contributor to wafer intra-field CD variation is the reticle CD variation. Current practice is that the input data needed to correct the effect of the reticle on the wafer CD is gathered using wafer exposures and SEM or scatterometry analysis. This approach consumes valuable scanner time and adds wafer costs. In this work we evaluate the potential for Intra-Field CD non-uniformity (CDU) correction based on aerial image reticle measurements for a complex 2D structure, including peripheral structures. The application selected is a 45nm rotated brick wall structure (active area DRAM). A total of 10 line / space structures (both horizontal and vertical) through pitch represent the periphery. Mask qualification has been performed using the newly developed Zeiss WLCD32 metrology tool, which measures wafer level CD on masks using aerial imaging technology. Excellent correlation is shown between intra-field wafer data and WLCD32 data. Furthermore, a comparison is made between the correction potential of ASML DoseMapper recipes based on wafer data and on WLCD32 mask data, indicating that the potential CDU improvement via both approaches is similar. Exposures with the resulting dose recipes have been used to confirm this predicted correction potential in a realistic setting.

As well as measuring CD, monitoring pattern profile is becoming important for semiconductor metrology. Illuminating the wafer and detecting the reflective light, reflective light intensity in the Fourier space includes the information of CD and pattern profile variation by form birefringence effect. CD change and profile variation could be detected separately for the actual wafer. Mathematical simulation is presented the background of our unique approach. The detail results of CD and pattern profile monitor is shown in this paper.

This work describes the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in IBM's 300mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity while sampling with sufficient frequency to ensure focus accuracy for stable production processes is described. The information reviewed includes: General AGILE implementation approaches; Sample focus correction contours for critical 45nm, 32nm, and 22nm applications; An outline of the IBM Advanced Process Control (APC) logic and system(s) that manage the focus correction sets; Long term, historical focus correction data for stable 45nm processes as well as development stage 32nm processes; Practical issues encountered and possible enhancements to the methodology.

Rapid, inline inspection of wafers and reticles for minimum pitch defects is expected to be a significant technical challenge at the 11nm node. With the possible future adoption of EUV lithography, increasingly exotic materials and complex device architectures, projecting end user requirements is a difficult feat 4 to 5 years out. The present work progresses through projections of these requirements and surveys the various options available to the industry, supported by microscopy simulations. The main conclusion is that the industry needs to support pathfinding projects to develop super-resolution techniques, wavelength scaling and highly multiplexed, high defect contrast ebeam inspection.

As technology node of memory devices is approaching around 30nm, the process window is becoming much narrower and production yield is getting more sensitive to tiny defects which used to be not, if ever, so critical. So it would be very hard to expect the same production yield as now in near future. It is possible to classify wafer defects into systematic and random defects. Systematic defects can be also divided into design related and process related defects. Narrow process window, generally, is thought to be the source of these systematic defects and we have to extend process window with Design for Manufacturing (DFM) and control process variation with Advanced Process Control (APC) to ensure the production yield. The sensitivity of random defects, however, has something to do with the smaller design rule itself. For example, the narrower spaces between lines are subject to bridge defects and the smaller lines, to pinch defects. Die to data base (DB) Design Based Metrology (DBM) has mainly been in use for detecting systematic defects and feedback to DFM and APC so far. We are trying to extend the application of DBM to random defects control. The conventional defect inspection systems are reaching its highest limit due to the low signal to noise ratio for extremely small feature sizes of below 40nm. It is found that Die to DB metrology tool is capable of detecting small but critical defects with reliability.

New techniques recently developed at the National Institute of Standards and Technology using bright-field optical tools are applied to signal-based defect analysis of features with dimensions well below the measurement wavelength. A key to this approach is engineering the illumination as a function of angle and analysis of the entire scattered field. In this paper we demonstrate advantages using this approach for die-to-die defect detection metrology. This methodology, scatterfield optical microscopy (SOM), is evaluated for defect inspection of several defect types defined by Sematech on the Defect Metrology Advisory Group (DMAG) intentional defect array (IDA) wafers. We also report the systematic evaluation of defect sensitivity as a function of illumination wavelength. Theoretical simulations are reported that were carried out using a fully three-dimensional finite difference time domain (FDTD) electromagnetic simulation package. Comprehensive modeling was completed investigating angle-resolved illumination to enhance the detection of several defect types from the IDA wafer designs. The defect types covered a variety of defects from the IDA designs. The simulations evaluate the SOM technique on defect sizes ranging from those currently measurable to those the industry considers difficult to measure. The simulations evaluated both the 65 nm IDA metal-1 M1 trench and the polysilicon stack and more recent 13 nm linewidth logic cells.

Considerable effort is directed towards the development of next-generation lithography processes, addressing the need for transistor densification to meet Moore's Law. The aggressive design rule shrinkage requires very tight process windows and induces various types of pattern failure with lithography process variations. Since the lithography process is critical in the wafer fabrication process, the requirements for high sensitivity defect detection in the lithography process becomes tighter as design rules shrink. Analysis of the root cause of the defects and of their interaction with various light sources and optics systems configurations for wafer inspection is essential for understanding the detection limits and requirements from advanced inspection systems targeting future lithography inspection applications. In this work, we present an analysis of wafer defects light scattering and detection for a variety of 3xnm design rule resist structures with various polarizations and optics configurations, at the visible, at UV and at DUV wavelengths. The analysis indicates on the defect scattering and inspection performance trends for a variety of resist structures and defect types, and shows that control of the polarization of the optical inspection system is critical for enhanced scattering and detection sensitivity. The analysis is performed also for the 2xnm and 1xnm design rules showing the advantages of polarized DUV illumination over unpolarized and visible illumination.

In this study, a 3x-nm after development inspection (ADI) wafer with focus exposure matrix (FEM) was inspected with both an advanced optical system and an advanced electron beam inspection (EBI) system, and the inspection results were carefully examined. We found that EBI can capture much more defects than optical system and it also can provide more information about within reticle shot defect distribution. It has high capture rate of certain critical defects that are insensitive to optical system, such as nano-bridges. We also studied the critical dimension (CD) variations caused by the optical inspection and EBI.

A case study of drastic photolithography defectivity reduction on i-line and Deep-UV (DUV) tools is presented. We show how this result is linked with reduction of Airborne Molecular Contamination (AMC) in clean room by combined installation of novel type of filters on tracks and on the recirculation air treatment. The root cause was identified to be the presence of acetic acid in clean room created by a reaction with the filters (mounted on track tools to exclude ammonia contamination of the process) and the photo solvent itself (here mainly 1-methoxy-2-propanol acetate: PGMEA). Crucial for the project success was the use of a real time monitoring tool to detect the sources of Volatile Organic Compounds (VOC). Finally, a model of chemical reaction of satellite defects creation is discussed based on a Time of Flight Static SIMS (TOF SSIMS) analysis together with new AMC specification for acetic acid for the photolithography area.

We established guidelines for accurately analyzing line-edge and line-width roughness (LER and LWR) basing on the recent discrete power-spectral-density (PSD) method. Extraction of correlation length ζ requires a plateau of PSD in a small-wave-number region. This requirement is met by letting a ratio of inspection length L to ζ be larger than 4π. Analysis errors caused by scanning-electron-microscope image noise are determined by ratios of measurement interval Δy to ζ and of noise-induced variance var(φ) to LWR variance var(w). The ratios need to be at most 20/35 and 1, respectively. var(φ) is reduced by averaging image pixels perpendicularly to lines. This averaging does not smooth LWR, unlike parallel averaging. Statistical noise, i.e. jaggy of PSDs, is another noise source that is caused by a finiteness of the number NFT of Fourier transforms averaged to obtain PSDs. The jaggy level decreases with NFT and with a decrease in Δy. Under the above Δy, NFT should preferably be 50 or larger. The total variance of this study was larger than the sum of var(w) and var(φ). The additional roughness results from a long-range correlation that exceeds the limit of this study. It will be analyzed in our forthcoming report.

LER and LWR have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly. In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.

Line edge roughness (LER) is an increasingly important issue as lithography scales down. Currently LER is usually measured using scanning electron microscopy (SEM) tools; however, using optical techniques to measure LER may have potential benefit due to less resist damage and higher throughput. In this paper, we explore the detection and potential measurement of LER using dark field spectroscopic reflectometry. We provide a proof of feasibility by showing LER spectra collected on several different applications, which behave consistently with scattering from small particles (Rayleigh) and decrease sharply with wavelength. Additionally, the dependence of the spectra on film thickness bears resemblance to thin film measurements. Finally, we also provide preliminary simulation results showing similar spectral characteristics to the measured spectra.

In this work, for the purpose of contact-hole process control, new metrics for contact-hole edge roughness (CER) are being proposed. The metrics are correlated to lithographic process variation which result in increased electric fields; a primary driver of time-dependent dielectric breakdown (TDDB). Electric field strength at the tip of spoke-shaped CER has been simulated; and new hole-feature metrics have been introduced. An algorithm for defining critical features like spoke angle, spoke length, etc has been defined. In addition, a method for identifying at-risk holes has been demonstrated. The number of spike holes can determine slight defocus conditions that are not detected though the conventional CER metrics. The newly proposed metrics can identify contact holes with a propensity for increased electric field concentration and are expected to improve contact-hole reliability in the sub-40-nm contact-hole process.

Methods of extracting information regarding critical dimensions (CD) in scanning electron microscopes (SEM) are currently based on image brightness. This brings significant uncertainty of the measured results because image brightness has a complex relation to the size and shape of feature, its material, geometry of the pattern as well as SEM setup. A model based extraction of CDs out of SEM images has been developed. The analysis is based on an understanding of physical principles involved in the formation of the SEM signal. Some parameters, such as beam voltage and materials, should be known to the operator as the input data along with the SEM image. The output results of the myCD software are contours of lines, linewidth at the top, bottom, and in the middle of the line, line edge roughnessess at each edge, line width roughness, and wall angles at each edge. In addition, averaged values over all lines present in the image are also displayed. The model based analysis of SEM images may considerably improve accuracy of CD measurements in SEM.

In contour metrology the CD-SEM (critical dimension scanning electron microscope) assigns a continuous boundary to extended features in an image. The boundary is typically assigned as a simple function of the signal intensity, for example by a brightness threshold or gradient. However, the neighborhood of different points along the feature boundary may vary considerably. Some parts of the boundary may have close neighboring features while others are relatively isolated. Neighboring features can obstruct the escape of secondary electrons. Varying proximity of neighbors therefore represents an influence on detected intensity. An intensity difference caused by a neighborhood difference can be incorrectly interpreted as a contour shift, for example when the contour passes from an isolated neighborhood to a dense one. The magnitude of this offset variation is estimated using images produced by JMONSEL, a Monte Carlo simulator of SEM secondary electron imaging, from simple model test patterns with varying neighborhoods. Similar structures were subsequently measured by both SEM and atomic force microscopy (AFM). Apparent shifts (i.e., errors) on the order of 0.5 nm to 1.0 nm for each edge were observed in both modeled and measured SEM images as compared to AFM when edge positions were assigned by using a fixed image brightness contour. Assignment of edges by brightness relative to the local background and local maximum brightness resulted in measurements that were less sensitive to neighborhood differences.

The aggressive design rules of deep sub-micron technology using Cu metal over Wplugs, makes process monitoring and characterization a real challenge. Lack of metal coverage above contact may cause yield degradation due to un-predicted contact resistance. Due to proximity effects and Optical-Proximity-Correction (OPC) restrictions, different layout configuration of metal-over-contact may results in different contact coverage by the metal. From metrology point-of-view, the ability to control process latitude of two constituent layers in the semiconductor process is critical. The basic way to develop and control Metal over Contact process with a CD-SEM is to measure the contact plugs through the metal trenches. This approach proposes a significant metrological challenge. There is no edge topography, only material contrast, and only part of the Contact can be seen. Hence, innovative algorithms and image processing techniques are required to accurately measure the metal-over-contact area coverage. In this paper, we demonstrate a reliable characterization and monitoring method. A dedicated test chip was designed for this purpose, having ~650 of different layout configurations and dimensions, in one nanometer variation. The methodology flow consists of using systematic Edge-Contour-Extraction (ECE). The physical parameters extracted from the ECE measurements analysis are used for several purposes: (i) identification of design-rule verification, (ii) contact resistance calculation based on the metal-over-contact coverage area, (iii) reliable feedback for OPC correction efficiency.

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, challenging mask defect dispositioning more than ever. To address these challenges in mask inspection and defect dispositioning, new mask inspection technologies have been developed that not only provide high resolution masks imaged at the same wavelength as the scanner, but that also provide aerial images by using both: software simulation and hardware emulation. The original mask patterns stored by the optics of mask inspection systems can be recovered using a patented algorithm based on the Level Set Method. More accurate lithography simulation models can be used to further evaluate defects on simulated resist patterns using the recovered mask pattern in high resolution and aerial mode. An automated defect classification based on lithography significance and local CD changes is also developed to disposition tens of thousands of potential defects in minutes, so that inspection throughput is not impacted.

Workhorse metrology such as CD-SEM is used during process development, process control, and optical proximity correction model generation and verification. Such metrology needs to be calibrated to handle various types of profiles encountered during IC fabrication. Reference metrology is used for calibration of workhorse metrology. There is an astounding need for sub-half and sub-quarter nanometer measurement uncertainty in the near future technology nodes as envisaged in the International Technology Roadmap for Semiconductors. In this regime of desired measurement uncertainty all metrology techniques are deemed limited and hybrid metrology appears promising to offer a solution. Hybrid metrology is the use of multiple metrology techniques, each with particular strength, to reduce the overall measurement uncertainty. CD-AFM makes use of a flared probe in order to scan the sidewalls and bottom of the pattern on a wafer to provide 3D profile and CD measurements at desired location on the profile. As the CD shrinks with technology nodes especially the space, the size of the AFM probe also needs to shrink while maintaining the flared geometry specifications. Unfortunately the fabrication of such probes is a challenge and new techniques are required to extend reference metrology to the smallest space and hole of interest. This paper proposes a reference system combining CD-AFM and patterning simulation model. This hybrid metrology system enables CD metrology in a space not measurable directly by conventional CD-AFM probe. The key idea is to use the successfully measured profile and CD information from the CD-AFM to calibrate or train the patterning simulation optical and resist model. Ability of this model to predict profile and CD measurement is verified on a physically measured dataset including cross sections and additional CD-AFM measurements. It is hypothesized that this model will be able to predict profile and CD measurements in otherwise immeasurable geometries. Being based on optics and materials fundamentals, this approach is presumed to be more accurate compared to mere extrapolation approach in use today. We report on the measurement uncertainty improvement with this approach. Situations with highest prediction confidence involve CD-AFM scanning resulting in partial information. For example, using carbon nanotube probes or CDP where there is little flaring of the tip, the CD-AFM cannot detect significant undercutting of the structure. Achieving agreement with the calibrated patterning model for measurement metrics such as height, top and middle CD permits the prediction of the bottom CD to be used as an authentic reference measurement.

The scatterometry or OCD (Optical CD) metrology technique has in recent years moved from being a general purpose CD metrology technique to one that addresses the metrology needs of process monitoring and control, where its strengths can be fully utilized. With the significant advancements that have been made in both hardware and software design, the setup time required to build complex models and solutions has been significantly reduced. Whilst the application of scatterometry to process control has clearly shown its merits, the question still arises as to how accurately the process corrections to feed forward or feedback for process control can be extracted? In this work we critically examine the accuracy of scatterometry with respect to process control by comparing three hardware platforms, on a simple litho stack. The impact of hardware design is discussed as well as the 'setup' of the modeled parameters on the final measurement result. It will be shown that informations extracted based on scatterometry measurements must be true to process variation and independent of the hardware design. Our results will show that the ability to use scatterometry effectively for process control ultimately lies in the ability to accurately determine the changes that have occurred in the process and to be able to extract appropriate process corrections for feedback or feed forward control; allowing these changes to be accurately corrected. To do this the metrology validation extends beyond the typical metrology metrics such as precision and TMU; metrology validation with respect to process control must encompass accurate determination of process corrections to ensure a process tool and/or process stays at the set point.

With the introduction of double patterning, overlay capability below 5nm is required for optical lithography density scaling to the 22nm node and beyond. Commensurate overlay metrology must enable dense sampling of all patterned area to control single-nanometer systematic sources of error among an increasing number of device layers. This translates to the need for sub-second measurement of microscopic targets representing multiple layers within a metrology tool field of view, all while improving accuracy. Blossom (BLO) is the overlay metrology of record for the IBM 32nm technology. As we will describe here, the densely packed array of layers represented in a single BLO target has enabled us to conduct within-field in-line sampling on our most critical layers. We will also report the significant improvements to metrology performance that have resulted from our migration of BLO technology to a new measurement platform. In addition, as 22nm development proceeds, we are shrinking our overlay targets further. A target suitable for within-chip insertion, a 10μm square micro-Blossom (μBLO) target, can accommodate up to 8 layers. Correlation of μBLO to BLO measurements on a layer pair shows excellent agreement, and despite an approximately 10X area shrink relative to BLO, the μBLO measurement uncertainty remains comfortably below 0.5nm. Our paper presents details of our target layout, measurement, and analysis approach. In addition, we detail data representative of overlay variation in state-of-the-art lithographic processes, along with our outlook for overlay metrology implementation for future technologies.

We have developed high-resolution grazing incidence x-ray diffraction (HRGIXD) pitch calibration system with wavelength of 0.1540593 nm (Cu K α₁ line). In order to ensure accuracy of this calibration system, we measured average pitch of a 100-nm pitch grating reference, which is being used for magnification calibration of a current critical-dimension scanning electron microscope (CD-SEM), and compared with the results of deep ultra violet (DUV) laser diffraction pitch calibration system with wavelength of 193 nm. The average pitch determined by the HRGIXD system agrees with that determined by the DUV laser diffraction system within the range of uncertainty. We measured average pitch of a fine 25-nm pitch grating, which will be used for magnification reference. In the DUV laser diffraction, wavelength of 193 nm no longer satisfies diffraction condition for the 25-nm pitch grating, because wavelength must be shorter than twice of the pitch size. On the other hand, wavelength of x-ray is much shorter than the pitch size. We have successfully detected more than ten sharp diffraction peaks corresponding to the 25-nm period. The average pitch of the grating is measured in very high-accuracy with standard uncertainty of less than 10 pm.

We have developed a new x-ray metrology for measuring surface periodic grating of semiconductor device pattern. X-rays irradiate surface of the device area with a shallow glancing angle, which is close to the critical angle of total external reflection of the surface material. The measured x-ray diffraction pattern is reflected to the average cross-sectional profile of the grating. The pattern made from SiO₂ on Si with100 nm-pitch is analyzed by the present x-ray metrology. The obtained profile, for example, line width, height of the grating and so on are well agreed with that observed by cross-sectional transmission electron microscopy. The wavelength of x-ray that we use is 0.154093 nm and it is enough shorter than the critical length of the grating structure, even when the line width becomes 10 nm or less. Therefore, the resolution of the x-ray metrology will be maintained good enough for the analysis that will be required in the future. In addition, x-ray metrology can be measure the cross-sectional profile with nondestructively due to hightransmissivity of x-rays for the materials. Furthermore, the optical parameter of the materials for x-ray is well established, therefore, x-ray metrology is applicable for any materials of device patterns without uncertain empirical parameters.

Grazing incidence small-angle x-ray scattering (GISAXS) is proposed as one of the candidates for characterizing cross section of nanostructure line grating pattern. GISAXS is expected as useful nondestructive tool for characterizing cross section. We developed GISAXS and evaluated the capability using the 4X nm resist line patterns and the 3X nm silicon gate line patterns. The GISAXS results are compared with TEM images to evaluate the reconstruction ability in cross section contour profile. The correlation is investigated between GISAXS and the reference tools such as CD-SEM and TEM in the values of CD, height and bottom corner radius. The static repeatability is also evaluated by performing measurement ten times. We report the results of GISAXS capability as cross sectional metrology tool in actual device of 4X and 3X generation.

The recently introduced helium ion microscope (HIM) is capable of imaging and fabrication of nanostructures thanks to its sub-nanometer sized ion probe. The unique interaction of the helium ions with the sample material provides very localized secondary electron emission, thus providing a valuable signal for high-resolution imaging as well as a mechanism for very precise nanofabrication. The low proximity effects, due to the low yield of backscattered ions and the confinement of the forward scattered ions into a narrow cone, enable patterning of ultra-dense sub-10 nm structures. This paper presents various nanofabrication results obtained with direct-write, with scanning helium ion beam lithography, and with helium ion beam induced deposition.

Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy provides a way of "looking" through silicon where microscopes based on visible wavelengths fail. Perhaps the most prevalent application of IR microscopes in 3D manufacturing is imaging sub-surface features at the interface of a bonded wafer pair. The ability to see through silicon using IR microscopes enables a variety of metrology techniques, including the overlay of circuit layers (e.g., metal 2 to via). IR microscopy is a non-destructive technique and, as such, it is an ideal candidate for in-line metrology for the bonded wafer pairs required for 3D interconnects. This paper reviews overlay metrology capability for an IR microscope. The ability to measure the overlay of bonded wafer pairs according to the 2009 International Technology Roadmap for Semiconductors (ITRS) is demonstrated. Overlay tolerances for a variety of copper interconnect test structures is predicted based on electrical designs, and overlay results are compared to electrical test results. The use of IR microscopy as an early indicator of electrical yield is clearly demonstrated.

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

A persistent industry problem impacting photomask yield and costs has been haze formation. The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Thus some capability will always be needed to remove haze on photomasks with their final pellicles mounted both at the manufacture and long term maintenance stages of a mask's lifetime. A novel technology is reviewed here which uses a dry (no chemical effluents) removal system to sweep the entire printable region of a pelliclized photomask to eliminate all removable haze regardless of the mask substrate materials or the presence of critical patterns. An operational process technique for this system and performance in removal is shown for haze located on the mask pattern surface. Finally, preliminary data from tool acceptance and preliminary use in a production environment will also be reviewed.

Defects on the backside of wafers can be either tool or process induced and can cause lithography-related issues such as focus deviation or chuck contamination. Tool induced scratches, process induced contamination, or residues on the back of wafers often have unique signatures, such as a repeatable scratch caused by wafer handling equipment or a chuck imprint on the backside of a wafer. Certain backside defect signatures such as large scratches or divots can contribute to wafer breakage or reliability issues. Spatial Pattern Recognition (SPR) is a method of comparing defect patterns at the wafer level with known defect signatures stored in a library that is created from process data. These defect signatures can represent systemic issues with process tools, handling equipment, or the process itself. This paper describes a backside inspection method for identifying wafers with both known and new spatial pattern signatures. By reporting the frequency of each signature category, process partitioning can efficiently trace the source of these problems. In addition, new defect signatures can be automatically learned and added to the library. The paper also includes examples of how this method was used to identify backside defect patterns caused by process and tool excursions in a 300mm fabricator.

Three years ago Entegris pioneered a novel method of controlling ammonium sulfate (AS) haze by maintaining 193 nm reticles in a low humidity environment. Since then, this approach has became an industry standard and is widely used in production fabs around the world. Based on analysis of practical applications in HVM fabs, this paper describes a successful approach to reticle haze control, outlines its critical elements and explains its limiting factors. In addition to actual fab data, the paper provides a large body of comparative experimental data on humidity dynamics in different reticle storage schemes and arrangements. With this data, the authors explain why some designs work much better than others and provide practical recommendations for lithography practitioners on haze control equipment selections and reticle management strategy development.

A new multipurpose instrument calibration standard has been released by NIST. This standard was developed to be used primarily for X and Y scale (or magnification) calibrations of scanning electron microscopes from less than 10 times magnification to more than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument field of view (FOV). This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration and testing of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be used for a number of other applications, some of which will be described in this publication.

The 2007 edition of ITRS has introduced a new metric for metrology quality assessment - measurement uncertainty (MU). The new metric has precision as one of many uncertainty components. Additional significant components are tool matching, sampling uncertainty and sample-to-sample bias variation. Sample dependent bias variation and, therefore, MU can be measured accurately only if a reference metrology (RM) is employed. RM is a must for achieving and verifying required today sub-nanometer MU of critical dimension (CD) metrology. To insure long-term performance of in-line metrology and reliable process control a simple but efficient way is suggested - employment of in-line RM system. SI-traceable CD AFM with sub-nanometer MU is a proper RM tool for the task.

We aim to develop and calibrate a set of step height standards to meet the range of steps useful for nanotechnology. Of particular interest to this community is the calibration of atomic force microscopes operating at their highest levels of magnification. In previous work we fabricated and calibrated step height standards consisting of the lattice steps on the (111) surface of single crystal Si and provided a recommended value of 312 pm ± 12 pm. In the current work we report traceable measurements of 1 nm step height specimens fabricated on the (0001) 4H-SiC surface. In this, we are seeking to fill in the range between the newly available 300 pm steps and 8 nm steps, which are the smallest available commercially. The step height measurements were performed using a calibrated atomic force microscope (C-AFM) calibrated with respect to the wavelength of light along all three axes of motion. Analysis of the measurements yields an average step height value of 0.981 nm with a combined standard uncertainty of ± 0.019 nm (k = 1), reasonably consistent with the expected value of 1.00851 nm derived from the parameters of the SiC crystal lattice.

Resist-on-silicon sub-50-nm critical dimension targets have been investigated using a 193 nm angle-resolved scatterfield microscope (ARSM). The illumination path of this microscope allows customization of the conjugate back focal plane (CBFP) while separate collection paths permit both high-magnification and Fourier-plane imaging. Aspects of the calibration of this microscope are presented. Full-field, Fourier-plane images are collected as individual targets are illuminated using a field-of-view smaller than the target size; the range of incident polar angles corresponds to the numerical aperture (NA) of the objective, NA = 0.08 to 0.74. Next, angle-resolved scatterfield high-magnification imaging of these same targets are acquired in a conical mounting configuration by scanning the 12 mm diameter CBFP with a 1 mm diameter aperture. The results of these measurements and the prospects for quantitative, simultaneous measurement of multiple targets are discussed.

We consider the effects of finite spectral bandwidth and numerical aperture in scatterometry measurements and discuss efficient integration methods based upon Gaussian quadrature in one dimension (for spectral bandwidth averaging) and two dimensions inside a circle (for numerical aperture averaging). Provided the wavelength is not near a Wood's anomaly for the grating, we find that the resulting methods converge very quickly to a level suitable for most measurement applications. In the vicinity of a Wood's anomaly, however, the methods provide rather poor behavior. We also describe a method that can be used to extract the effective spectral bandwidth and numerical aperture for a scatterometry tool. We find that accounting for spectral bandwidth and numerical aperture is necessary to obtain satisfactory results in scatterometry.

The ability to extract critical parameters using scatterometry depends on the parameter sensitivity and correlation at different wavelengths. These, in turn, determine the key metrics: accuracy, precision, and tool-to-tool matching. Parameter sensitivity and correlation can vary drastically, depending on whether the oblique incident light beam is parallel (azimuth angle = 90 degrees), perpendicular (azimuth angle = 0 degrees), or at an intermediate angle to the measured structures. In this paper, we explore the use of both variable- and multiple-azimuth (AZ) (or multi-AZ) angle spectroscopic ellipsometry (SE) to optimize the measurement performance for different applications. The first example compares the sensitivity and results using SE at 0 and 90 degree AZ angles for a BEOL post-litho metal trench application. We observe up to a sixfold improvement in key metrics for critical parameters using 90 degree over 0 degree AZ angle spectra. The second example illustrates the benefits of a multiple-AZ angle approach to extract critical parameters for a two-dimensional logic High-K Metal Gate (HKMG) structure. Typically, this approach simultaneously fits two sets of SE spectra collected from the same location on the wafer at different AZ angles with the same physical model. This helps both validate and decorrelate critical parameters, enabling robust measurements. Results show that, for this application, the measurement performance metrics for each critical parameter are improved in almost every case.

Optical properties (n&k) of the material films under measurement are commonly assumed invariant and fixed in scatterometry modeling. This assumption keeps the modeling simple by limiting the number of floating parameters in the model. Such scatterometry measurement has the potential to measure with high precision some of the profile parameters (CD, Sidewall angle). The question is: if the optical properties modeled as "fixed" are actually changing - would this modeling assumption impact the accuracy of reported geometrical parameters? Using the example of a resist profile measurement, we quantify the "bias" effect of un-modeled variation of optical properties on the accuracy of the reported geometry by utilizing a traditional fixed n&k model. With a second model we float an additional optical parameter and lower the bias of the reported values - at the expense of slightly increased "noise" of the measurement (more floating parameters - less precision). Finally, we extend our multi-stack approach (previously introduced as enabler to the product-driven materials characterization methodology) to augment the spectral information and increase both precision and accuracy through the simultaneous modeling of multiple targets

In this work we report the results of the optical characterization of a periodic grating carried out with a probe spot size larger than the sample grating "box". The measured depolarizing Mueller matrices resulting from incoherent superposition of the optical responses of the grating and substrate were filtered by using the eigenvalues decomposition method. The retrieved Mueller matrices of the grating alone were fitted using rigorous coupled-wave method and the standard trapezoidal model with three parameters: the middle line-width (CD), the grating depth and the side-wall angle. The results are shown for all measured azimuthal angles and compared with reference values taken on a similar grating on the same wafer, in the usual conditions (beam spot inside the grating). The observed stability of the parameters very closely coincides with the reference grating except for some azimuthal angles, where the grating contributed only 5% of the signal. The overall dispersion of the parameters is within the few nanometers from the statistical mean value, a performance comparable to that of standard grating characterizations with the probe beam illuminating only the grating.

DPT overlay errors result in CD distortions and CD non-uniformity leads to overlay errors demanding increased critical dimension uniformity (CDU) and improved overlay control. Scatterometry techniques are used to characterize the CD uniformity, focus and dose control. We will present CD distribution (CDU) and profile characterization for spacer double patterning structures by advanced scatterometry methods. Our result will include NISR, and spectroscopic ellipsometry (SE) characterization of CDU sensitivity in spacer double patterning stack. We will further show the results of spacer DP structures by NISR and SE measurements. Metrology comparison at various process steps including litho, etch and spacer and validation of CDU and profile; all benchmarked against traditional CDSEM measurements.

The novel calibration method of sub-nanometer accuracy for the line width measurement using STEM images is proposed to calibrate CD-SEM line width measurements. In accordance with the proposed method, the traceability and reference metrology of line width standards are established using Si lattice structures. First, we define the edge of a line as the end of Si lattice structure as the interface between Si lattice and oxide film. Second, an image magnification and inclination angles are calculated using 2D Fourier analysis of a STEM image. Third, the edge positions of the line are detected after the novel noise reduction method using averaging by Si lattice patterns. Then, the uncertainty of the line width measurement is evaluated with the uncertainty contributors of pixel size, edge detections and repeatability. Using the proposed method, the expanded uncertainty less than 0.5 nm for the line width of 45 nm is established.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized features. This work was extended in yet another paper in which we presented a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

We present the Monte Carlo simulation program MCSEM, developed at the Physikalisch-Technische Bundesanstalt (PTB), Germany, for the simulation of Scanning Electron Microscopy (SEM) image formation at arbitrary specimen structures (e.g. layout structures of wafers or photomasks). The program simulates the different stages of the SEM image formation process: the probe forming, the probe-sample interaction and the detection process. A modular program structure is used for an easy adaptation of the program to new simulation tasks. Arbitrarily shaped 3D structured specimen models can be applied and different electron probe shapes are modeled. Various physical models for electron scattering in solid state material are included. Secondary electron (SE) detection modeling is based on SE raytracing, detectors for backscattered electrons (BSE) and transmitted electrons (TE) are also available. An electromagnetic field solver is used to simulate charging of the specimen and the transport of the SE within the electromagnetic field. Some examples of simulation results are presented together with comparisons with experimental results.