As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic
effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER
variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and
exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices,
attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device
performance and die yield.
Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area.
In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of
Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM
and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The
method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light
from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer
inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a
successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high
sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can
help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run.
The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or
Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values,
that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.